An investigation of sensitization conditions and test effectiveness for CMOS faults

Testing of digital circuits ensures functionality and reliability of the circuits. Previous research has addressed the inadequacies of conventional test methods based on line stuck-at faults in testing CMOS circuits and has proposed new test methods. In this research, the effectiveness of propagation delay testing for open and short faults and supply current monitoring for short faults is investigated. Representative circuits are modeled and simulated over a wide range of fault severities. Factors, such as circuit and fault features, that affect test effectiveness are evaluated and analyzed. From the results, general conclusions are drawn and future research is proposed.

Name thesis:degree_name

Master of Science

Level thesis:degree_level

masters

Discipline thesis:degree_discipline

Electrical Engineering

Department dc:contributor.department

Electrical Engineering

Grantor dc:publisher

Virginia Tech

Year dc:date.issued

1989

Author dc:creator

• Koe, Wern-Yan

Chair dc:contributor.committeechair

• Midkiff, Scott F.

Committee members dc:contributor.committeemember

• Ha, Dong Sam
• Tront, Joseph G.

Statement dc:rights

• In Copyright

Licence dc:rights.uri

• http://rightsstatements.org/vocab/InC/1.0/

Language dc:language.iso

en

Dc Identifier Other

etd-11292012-040100

OAI identifier oai:identifier

oai:vtechworks.lib.vt.edu:10919/46045