{"id":{"repo_id":"vt","oai_identifier":"oai:vtechworks.lib.vt.edu:10919/45596"},"canonical_url":"https://search.dev.ndltd.org/etd/vt/oai:vtechworks.lib.vt.edu:10919/45596","repository":{"repo_id":"vt","name":"Virginia Tech","base_url":"https://vtechworks.lib.vt.edu/oai/request"},"display":{"title":"Rapid development of VHDL behavioral models","abstract":"The enhancement of a CAD tool called Modeler's Assistant is discussed. This tool allows VHDL behavioral models to be developed more rapidly than with traditional techniques. The limitations present in the previous version of the tool (Version 2) are discussed. The correction of these limitations and the enhancement of Modeler's Assistant are the focus of the work described in this thesis. New features present in the enhanced version of Modeler's Assistant (Version 3) include the ability to create and maintain a library of parameterized process primitives and the ability to graphically represent hierarchy in VHDL behavioral models through the use of supernodes. Other enhancements that allow more features of the VHDL language to be used in Modeler's Assistant are described. Several examples that illustrate the use of these enhanced features are presented.","abstract_html":"The enhancement of a CAD tool called Modeler's Assistant is discussed. This tool allows VHDL behavioral models to be developed more rapidly than with traditional techniques. The limitations present in the previous version of the tool (Version 2) are discussed. The correction of these limitations and the enhancement of Modeler's Assistant are the focus of the work described in this thesis. New features present in the enhanced version of Modeler's Assistant (Version 3) include the ability to create and maintain a library of parameterized process primitives and the ability to graphically represent hierarchy in VHDL behavioral models through the use of supernodes. Other enhancements that allow more features of the VHDL language to be used in Modeler's Assistant are described. Several examples that illustrate the use of these enhanced features are presented.","abstract_has_math":false,"creators":["Wright, Philip A."],"institution":"Virginia Tech","degree_name":"Master of Science","degree_level":"masters","degree_discipline":"Electrical Engineering","degree_department":"Electrical Engineering","school":null,"contributors":[],"advisors":[],"committee_chairs":[],"committee_members":[],"year":1992,"date_issued":"1992","date_published":"1992","updated_at":"2026-07-22T22:18:53Z","subjects":[],"languages":["en"],"rights":["In Copyright"],"rights_urls":["http://rightsstatements.org/vocab/InC/1.0/"],"identifier_entries":[{"key":"dc:identifier.other","label":"Dc Identifier Other","values":["etd-11102009-020056"],"render_values":[{"text":"etd-11102009-020056","href":null,"code":true}]}]},"links":{"outbound_url":"http://hdl.handle.net/10919/45596","outbound_label":"Handle","outbound_source":"dc:identifier.uri"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor.department","label":"Department","values":["Electrical Engineering"]},{"key":"dc:creator","label":"Author","values":["Wright, Philip A."]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date.accessioned","label":"Dc Date Accessioned","values":["2014-03-14T21:49:23Z"]},{"key":"dc:date.available","label":"Dc Date Available","values":["2014-03-14T21:49:23Z","2009-11-10"]},{"key":"dc:date.issued","label":"Date","values":["1992"]},{"key":"dc:publisher","label":"Institution","values":["Virginia Tech"]},{"key":"dc:type","label":"Dc Type","values":["Thesis"]},{"key":"dc:type.dcmitype","label":"Dc Type Dcmitype","values":["Text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical Engineering"]},{"key":"thesis:degree_level","label":"Degree Level","values":["masters"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Master of Science"]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["Virginia Polytechnic Institute and State University"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language.iso","label":"Language (ISO)","values":["en"]},{"key":"dc:rights","label":"Dc Rights","values":["In Copyright"]},{"key":"dc:rights.uri","label":"Rights URI","values":["http://rightsstatements.org/vocab/InC/1.0/"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier.other","label":"Dc Identifier Other","values":["etd-11102009-020056"]},{"key":"dc:identifier.uri","label":"Identifier URI","values":["http://hdl.handle.net/10919/45596"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description.abstract","label":"Abstract","values":["The enhancement of a CAD tool called Modeler's Assistant is discussed. This tool allows VHDL behavioral models to be developed more rapidly than with traditional techniques. The limitations present in the previous version of the tool (Version 2) are discussed. The correction of these limitations and the enhancement of Modeler's Assistant are the focus of the work described in this thesis. New features present in the enhanced version of Modeler's Assistant (Version 3) include the ability to create and maintain a library of parameterized process primitives and the ability to graphically represent hierarchy in VHDL behavioral models through the use of supernodes. Other enhancements that allow more features of the VHDL language to be used in Modeler's Assistant are described. Several examples that illustrate the use of these enhanced features are presented."]},{"key":"dc:description.degree","label":"Dc Description Degree","values":["Master of Science"]},{"key":"dc:format.medium","label":"Dc Format Medium","values":["BTD"]},{"key":"dc:format.mimetype","label":"Dc Format Mimetype","values":["application/pdf"]},{"key":"dc:title","label":"Title","values":["Rapid development of VHDL behavioral models"]}]}],"canonical_facts":{"dc:contributor.department":["Electrical Engineering"],"dc:creator":["Wright, Philip A."],"dc:date.accessioned":["2014-03-14T21:49:23Z"],"dc:date.available":["2014-03-14T21:49:23Z","2009-11-10"],"dc:date.issued":["1992"],"dc:description.abstract":["The enhancement of a CAD tool called Modeler's Assistant is discussed. This tool allows VHDL behavioral models to be developed more rapidly than with traditional techniques. The limitations present in the previous version of the tool (Version 2) are discussed. The correction of these limitations and the enhancement of Modeler's Assistant are the focus of the work described in this thesis. New features present in the enhanced version of Modeler's Assistant (Version 3) include the ability to create and maintain a library of parameterized process primitives and the ability to graphically represent hierarchy in VHDL behavioral models through the use of supernodes. Other enhancements that allow more features of the VHDL language to be used in Modeler's Assistant are described. Several examples that illustrate the use of these enhanced features are presented."],"dc:description.degree":["Master of Science"],"dc:format.medium":["BTD"],"dc:format.mimetype":["application/pdf"],"dc:identifier.other":["etd-11102009-020056"],"dc:identifier.uri":["http://hdl.handle.net/10919/45596"],"dc:language.iso":["en"],"dc:publisher":["Virginia Tech"],"dc:rights":["In Copyright"],"dc:rights.uri":["http://rightsstatements.org/vocab/InC/1.0/"],"dc:title":["Rapid development of VHDL behavioral models"],"dc:type":["Thesis"],"dc:type.dcmitype":["Text"],"thesis:degree_discipline":["Electrical Engineering"],"thesis:degree_level":["masters"],"thesis:degree_name":["Master of Science"],"thesis:institution_name":["Virginia Polytechnic Institute and State University"]},"updated_at":"2026-07-22T22:18:53Z"}