{"id":{"repo_id":"vt","oai_identifier":"oai:vtechworks.lib.vt.edu:10919/45450"},"canonical_url":"https://search.dev.ndltd.org/etd/vt/oai:vtechworks.lib.vt.edu:10919/45450","repository":{"repo_id":"vt","name":"Virginia Tech","base_url":"https://vtechworks.lib.vt.edu/oai/request"},"display":{"title":"Analysis and design of a novel controller architecture and design methodology for speed control of switched reluctance motors","abstract":"This paper presents a novel controller architecture and speed control design methodology suitable for low cost, low performance switched reluctance motor drives. By utilizing inexpensive components in a simple, compact architecture, a low cost controller is developed which achieves a performance level similar to many high performance controllers. A speed control design methodology is established and analyzed based on the linearized small signal model of the switched reluctance motor. This unique control methodology is simple and provides a starting point for further research into speed/current controller parameter design for switched reluctance motors. The analysis, design and realization of the speed controller are presented. The derivation of the design methodology for speed controlled, switched reluctance motor drives is discussed, along with computer simulations for verification. Experimental results utilizing the proposed architecture and design methodology verify the control design and performance capabilities of the speed controller system.","abstract_html":"This paper presents a novel controller architecture and speed control design methodology suitable for low cost, low performance switched reluctance motor drives. By utilizing inexpensive components in a simple, compact architecture, a low cost controller is developed which achieves a performance level similar to many high performance controllers. A speed control design methodology is established and analyzed based on the linearized small signal model of the switched reluctance motor. This unique control methodology is simple and provides a starting point for further research into speed/current controller parameter design for switched reluctance motors. The analysis, design and realization of the speed controller are presented. The derivation of the design methodology for speed controlled, switched reluctance motor drives is discussed, along with computer simulations for verification. Experimental results utilizing the proposed architecture and design methodology verify the control design and performance capabilities of the speed controller system.","abstract_has_math":false,"creators":["Jackson, Terry W."],"institution":"Virginia Tech","degree_name":"Master of Science","degree_level":"masters","degree_discipline":"Electrical Engineering","degree_department":"Electrical Engineering","school":null,"contributors":[],"advisors":[],"committee_chairs":["Ramu, Krishnan"],"committee_members":["Nunnally, Charles E.","VanLandingham, Hugh F."],"year":1996,"date_issued":"1996-07-05","date_published":"1996-07-05","updated_at":"2026-07-22T22:19:51Z","subjects":["switched reluctance motor","electric drives","linearization","controller","control design"],"languages":["en"],"rights":["In Copyright"],"rights_urls":["http://rightsstatements.org/vocab/InC/1.0/"],"identifier_entries":[{"key":"dc:identifier.other","label":"Dc Identifier Other","values":["etd-11072008-063133"],"render_values":[{"text":"etd-11072008-063133","href":null,"code":true}]}]},"links":{"outbound_url":"http://hdl.handle.net/10919/45450","outbound_label":"Handle","outbound_source":"dc:identifier.uri"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor.committeechair","label":"Committee Chair","values":["Ramu, Krishnan"]},{"key":"dc:contributor.committeemember","label":"Committee Member","values":["Nunnally, Charles E.","VanLandingham, Hugh F."]},{"key":"dc:contributor.department","label":"Department","values":["Electrical Engineering"]},{"key":"dc:creator","label":"Author","values":["Jackson, Terry W."]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date.accessioned","label":"Dc Date Accessioned","values":["2014-03-14T21:48:59Z"]},{"key":"dc:date.available","label":"Dc Date Available","values":["2014-03-14T21:48:59Z","2008-11-07"]},{"key":"dc:date.issued","label":"Date","values":["1996-07-05"]},{"key":"dc:publisher","label":"Institution","values":["Virginia Tech"]},{"key":"dc:type","label":"Dc Type","values":["Thesis"]},{"key":"dc:type.dcmitype","label":"Dc Type Dcmitype","values":["Text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical Engineering"]},{"key":"thesis:degree_level","label":"Degree Level","values":["masters"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Master of Science"]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["Virginia Polytechnic Institute and State University"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["switched reluctance motor","electric drives","linearization","controller","control design"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language.iso","label":"Language (ISO)","values":["en"]},{"key":"dc:rights","label":"Dc Rights","values":["In Copyright"]},{"key":"dc:rights.uri","label":"Rights URI","values":["http://rightsstatements.org/vocab/InC/1.0/"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier.other","label":"Dc Identifier Other","values":["etd-11072008-063133"]},{"key":"dc:identifier.uri","label":"Identifier URI","values":["http://hdl.handle.net/10919/45450"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description.abstract","label":"Abstract","values":["This paper presents a novel controller architecture and speed control design methodology suitable for low cost, low performance switched reluctance motor drives. By utilizing inexpensive components in a simple, compact architecture, a low cost controller is developed which achieves a performance level similar to many high performance controllers. A speed control design methodology is established and analyzed based on the linearized small signal model of the switched reluctance motor. This unique control methodology is simple and provides a starting point for further research into speed/current controller parameter design for switched reluctance motors. The analysis, design and realization of the speed controller are presented. The derivation of the design methodology for speed controlled, switched reluctance motor drives is discussed, along with computer simulations for verification. Experimental results utilizing the proposed architecture and design methodology verify the control design and performance capabilities of the speed controller system."]},{"key":"dc:description.degree","label":"Dc Description Degree","values":["Master of Science"]},{"key":"dc:format.medium","label":"Dc Format Medium","values":["BTD"]},{"key":"dc:format.mimetype","label":"Dc Format Mimetype","values":["application/pdf"]},{"key":"dc:title","label":"Title","values":["Analysis and design of a novel controller architecture and design methodology for speed control of switched reluctance motors"]}]}],"canonical_facts":{"dc:contributor.committeechair":["Ramu, Krishnan"],"dc:contributor.committeemember":["Nunnally, Charles E.","VanLandingham, Hugh F."],"dc:contributor.department":["Electrical Engineering"],"dc:creator":["Jackson, Terry W."],"dc:date.accessioned":["2014-03-14T21:48:59Z"],"dc:date.available":["2014-03-14T21:48:59Z","2008-11-07"],"dc:date.issued":["1996-07-05"],"dc:description.abstract":["This paper presents a novel controller architecture and speed control design methodology suitable for low cost, low performance switched reluctance motor drives. By utilizing inexpensive components in a simple, compact architecture, a low cost controller is developed which achieves a performance level similar to many high performance controllers. A speed control design methodology is established and analyzed based on the linearized small signal model of the switched reluctance motor. This unique control methodology is simple and provides a starting point for further research into speed/current controller parameter design for switched reluctance motors. The analysis, design and realization of the speed controller are presented. The derivation of the design methodology for speed controlled, switched reluctance motor drives is discussed, along with computer simulations for verification. Experimental results utilizing the proposed architecture and design methodology verify the control design and performance capabilities of the speed controller system."],"dc:description.degree":["Master of Science"],"dc:format.medium":["BTD"],"dc:format.mimetype":["application/pdf"],"dc:identifier.other":["etd-11072008-063133"],"dc:identifier.uri":["http://hdl.handle.net/10919/45450"],"dc:language.iso":["en"],"dc:publisher":["Virginia Tech"],"dc:rights":["In Copyright"],"dc:rights.uri":["http://rightsstatements.org/vocab/InC/1.0/"],"dc:subject":["switched reluctance motor","electric drives","linearization","controller","control design"],"dc:title":["Analysis and design of a novel controller architecture and design methodology for speed control of switched reluctance motors"],"dc:type":["Thesis"],"dc:type.dcmitype":["Text"],"thesis:degree_discipline":["Electrical Engineering"],"thesis:degree_level":["masters"],"thesis:degree_name":["Master of Science"],"thesis:institution_name":["Virginia Polytechnic Institute and State University"]},"updated_at":"2026-07-22T22:19:51Z"}