Hazard detection with VHDL in combinational logic circuits with fixed delays

Timing hazards are common problems found in logic circuits. A new integrated hazard detection system (HDS), which is implemented in VHDL, is proposed to detect the static, the dynamic, and the function hazards in any logic circuit that is described structurally in VHDL. This system adopts the IEEE VHDL Model Standard Group 1076-1164 Nine-Valued Multiple-Valued Logic package. Without any designer-supplied arbitrary input test patterns, the system predicts which input combinations will cause hazards, reports what type of hazards, and provides detailed timing information on the hazards in the combinational logic circuit with fixed gate delays.

Name thesis:degree_name

Master of Science

Level thesis:degree_level

masters

Discipline thesis:degree_discipline

Electrical Engineering

Department dc:contributor.department

Electrical Engineering

Grantor dc:publisher

Virginia Tech

Year dc:date.issued

1992

Author dc:creator

• Chu, Ming-Cheung

Chair dc:contributor.committeechair

• Armstrong, James R.

Committee members dc:contributor.committeemember

• Gray, Festus Gail
• Ha, Dong Sam

Statement dc:rights

• In Copyright

Licence dc:rights.uri

• http://rightsstatements.org/vocab/InC/1.0/

Language dc:language.iso

en

Dc Identifier Other

etd-10062009-020040

OAI identifier oai:identifier

oai:vtechworks.lib.vt.edu:10919/45005