Simulation and implementation of fixed-point digital filter structures

The purpose of this research is to develop a fixed-point arithmetic model based on a common general purpose Digital Signal Processor (DSP). A detailed non-linear model is developed to emulate the convergent (un-biased) rounding process performed by the Motorola DSP56002 fixed-point DSP. This model is incorporated into several different filter structures and compared to the linear stochastic simulation and the actual hardware implementation. It turns out that the convergent rounding operation has an insignificant effect on the overall roundoff noise power. The Direct Form, Section Optimal and MA Lattice forms are studied. F or these structures, Matlab routines are developed to automate the process of fixed-point scaling and DSP56002 code generation. Each structure's non-linear simulation is validated using two filter examples. The scaling and simulation routines allow the filter designer to investigate the finite word length performance of various structures, scaling norms, overflow safety factors, and word lengths to determine the best filter parameters prior to hardware implementation.

Name thesis:degree_name

Master of Science

Level thesis:degree_level

masters

Discipline thesis:degree_discipline

Electrical Engineering

Department dc:contributor.department

Electrical Engineering

Grantor dc:publisher

Virginia Tech

Year dc:date.issued

1995

Author dc:creator

• Bailey, Daniel A.

Chair dc:contributor.committeechair

• Beex, A. A. Louis

Committee members dc:contributor.committeemember

• Reed, Jeffrey H.
• VanLandingham, Hugh F.

• Digital Signal Processor

Statement dc:rights

• In Copyright

Licence dc:rights.uri

• http://rightsstatements.org/vocab/InC/1.0/

Language dc:language.iso

en

Dc Identifier Other

etd-07112009-040546

OAI identifier oai:identifier

oai:vtechworks.lib.vt.edu:10919/43697