TENOR: an ATPG for transition faults in combinational circuits

Delay fault testing of high speed VLSI circuits is becoming increasingly important. This thesis presents an Automatic Test Pattern Generator (ATPG), called TENOR, for transition faults. Transition faults are a special case of gate delay faults. Test generation is based on the FAN algorithm. The approach taken in this thesis is to map a transition fault into two stuck-at faults, and then generate test patterns for the stuck-at faults. A fault simulator, based on parallel pattern single fault propagation, was also developed. The problem of generating both non-robust and robust tests has been addressed. Experimental results indicate that TENOR is one of the fastest ATPGs among similar previous works, with comparable fault coverage. Experiments were also done to determine the effectiveness of stuck-at test sets and random test patterns in detecting transition faults.

Name thesis:degree_name

Master of Science

Level thesis:degree_level

masters

Discipline thesis:degree_discipline

Electrical Engineering

Department dc:contributor.department

Electrical Engineering

Grantor dc:publisher

Virginia Tech

Year dc:date.issued

1994

Author dc:creator

• Tyagi, Dhawal

Statement dc:rights

• In Copyright

Licence dc:rights.uri

• http://rightsstatements.org/vocab/InC/1.0/

Language dc:language.iso

en

Dc Identifier Other

etd-06302009-040525

OAI identifier oai:identifier

oai:vtechworks.lib.vt.edu:10919/43515