{"id":{"repo_id":"vt","oai_identifier":"oai:vtechworks.lib.vt.edu:10919/42401"},"canonical_url":"https://search.dev.ndltd.org/etd/vt/oai:vtechworks.lib.vt.edu:10919/42401","repository":{"repo_id":"vt","name":"Virginia Tech","base_url":"https://vtechworks.lib.vt.edu/oai/request"},"display":{"title":"Mapping conceptual graphs to primitive VHDL processes","abstract":"This thesis discusses an algorithm for mapping conceptual graphs to primitive VHDL processes. The behavior of each primitive process is stored in the form of a schema. The algorithm identifies concepts in the input referring to MODAS (Modeler's Assistant) process primitives and maps their schemata to the input conceptual graph. The results of the mapping are used to modify the primitive process's VHDL and instantiate a new process. A library of schemata for the primitive processes in MODAS has been developed. This algorithm has been implemented in the CGVHDL Linker program. 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