{"id":{"repo_id":"vt","oai_identifier":"oai:vtechworks.lib.vt.edu:10919/42221"},"canonical_url":"https://search.dev.ndltd.org/etd/vt/oai:vtechworks.lib.vt.edu:10919/42221","repository":{"repo_id":"vt","name":"Virginia Tech","base_url":"https://vtechworks.lib.vt.edu/oai/request"},"display":{"title":"Susceptibility evaluation of combinational logic in VLSI circuits","abstract":"A number of errors occur in digital systems operating in a harsh radiation environment. These errors are due to transient faults which may cause a temporary change in the state of the system without any permanent damage. These transient faults are referred to as Single Event Upsets (SEUs). Because of their random and non-recurring nature, such faults are very difficult to detect and hence are of source of great concern. This thesis examines the logical response of combinational logic circuits to SEUs. Time domain analyses of a large number of circuits attempts to determine the affect of an SEU on a flip-flop which might lay at the end of a chain of combinational logic gates. In this way, the concept of an upset window, as it pertains to different types of logic gates is introduced. The results of the simulations carried out on various blocks of combinational logic are discussed. A program called SUPER (SUsceptibility PrEdiction pRogram) is developed. SUPER predicts the probability of a circuit fault occurring given that a cosmic ray with certain energy characteristics impinges on an arbitrary point within an IC. IC. The input variables to SUPER include the radiation level, the duration of the radiation, the types of gates the radiation affects, the signal path, the type of voltage pulse that the radiation produces (rising or falling) and the time (with respect to the clock pulse) that the radiation is incident on the circuit. The output of SUPER consists of a prediction as to whether or not the incident radiation causes a change in the output of a flip-flop.","abstract_html":"A number of errors occur in digital systems operating in a harsh radiation environment. These errors are due to transient faults which may cause a temporary change in the state of the system without any permanent damage. These transient faults are referred to as Single Event Upsets (SEUs). Because of their random and non-recurring nature, such faults are very difficult to detect and hence are of source of great concern. This thesis examines the logical response of combinational logic circuits to SEUs. Time domain analyses of a large number of circuits attempts to determine the affect of an SEU on a flip-flop which might lay at the end of a chain of combinational logic gates. In this way, the concept of an upset window, as it pertains to different types of logic gates is introduced. The results of the simulations carried out on various blocks of combinational logic are discussed. A program called SUPER (SUsceptibility PrEdiction pRogram) is developed. SUPER predicts the probability of a circuit fault occurring given that a cosmic ray with certain energy characteristics impinges on an arbitrary point within an IC. IC. The input variables to SUPER include the radiation level, the duration of the radiation, the types of gates the radiation affects, the signal path, the type of voltage pulse that the radiation produces (rising or falling) and the time (with respect to the clock pulse) that the radiation is incident on the circuit. The output of SUPER consists of a prediction as to whether or not the incident radiation causes a change in the output of a flip-flop.","abstract_has_math":false,"creators":["Modi, Manish Harsukh"],"institution":"Virginia Tech","degree_name":"Master of Science","degree_level":"masters","degree_discipline":"Electrical Engineering","degree_department":"Electrical Engineering","school":null,"contributors":[],"advisors":[],"committee_chairs":[],"committee_members":[],"year":1990,"date_issued":"1990","date_published":"1990","updated_at":"2026-07-22T22:20:41Z","subjects":[],"languages":["en"],"rights":["In Copyright"],"rights_urls":["http://rightsstatements.org/vocab/InC/1.0/"],"identifier_entries":[{"key":"dc:identifier.other","label":"Dc Identifier Other","values":["etd-04252009-040716"],"render_values":[{"text":"etd-04252009-040716","href":null,"code":true}]}]},"links":{"outbound_url":"http://hdl.handle.net/10919/42221","outbound_label":"Handle","outbound_source":"dc:identifier.uri"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor.department","label":"Department","values":["Electrical Engineering"]},{"key":"dc:creator","label":"Author","values":["Modi, Manish Harsukh"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date.accessioned","label":"Dc Date Accessioned","values":["2014-03-14T21:34:29Z"]},{"key":"dc:date.available","label":"Dc Date Available","values":["2014-03-14T21:34:29Z","2009-04-25"]},{"key":"dc:date.issued","label":"Date","values":["1990"]},{"key":"dc:publisher","label":"Institution","values":["Virginia Tech"]},{"key":"dc:type","label":"Dc Type","values":["Thesis"]},{"key":"dc:type.dcmitype","label":"Dc Type Dcmitype","values":["Text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical Engineering"]},{"key":"thesis:degree_level","label":"Degree Level","values":["masters"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Master of Science"]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["Virginia Polytechnic Institute and State University"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language.iso","label":"Language (ISO)","values":["en"]},{"key":"dc:rights","label":"Dc Rights","values":["In Copyright"]},{"key":"dc:rights.uri","label":"Rights URI","values":["http://rightsstatements.org/vocab/InC/1.0/"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier.other","label":"Dc Identifier Other","values":["etd-04252009-040716"]},{"key":"dc:identifier.uri","label":"Identifier URI","values":["http://hdl.handle.net/10919/42221"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description.abstract","label":"Abstract","values":["A number of errors occur in digital systems operating in a harsh radiation environment. These errors are due to transient faults which may cause a temporary change in the state of the system without any permanent damage. These transient faults are referred to as Single Event Upsets (SEUs). Because of their random and non-recurring nature, such faults are very difficult to detect and hence are of source of great concern. This thesis examines the logical response of combinational logic circuits to SEUs. Time domain analyses of a large number of circuits attempts to determine the affect of an SEU on a flip-flop which might lay at the end of a chain of combinational logic gates. In this way, the concept of an upset window, as it pertains to different types of logic gates is introduced. The results of the simulations carried out on various blocks of combinational logic are discussed. A program called SUPER (SUsceptibility PrEdiction pRogram) is developed. SUPER predicts the probability of a circuit fault occurring given that a cosmic ray with certain energy characteristics impinges on an arbitrary point within an IC. IC. The input variables to SUPER include the radiation level, the duration of the radiation, the types of gates the radiation affects, the signal path, the type of voltage pulse that the radiation produces (rising or falling) and the time (with respect to the clock pulse) that the radiation is incident on the circuit. The output of SUPER consists of a prediction as to whether or not the incident radiation causes a change in the output of a flip-flop."]},{"key":"dc:description.degree","label":"Dc Description Degree","values":["Master of Science"]},{"key":"dc:format.medium","label":"Dc Format Medium","values":["BTD"]},{"key":"dc:format.mimetype","label":"Dc Format Mimetype","values":["application/pdf"]},{"key":"dc:title","label":"Title","values":["Susceptibility evaluation of combinational logic in VLSI circuits"]}]}],"canonical_facts":{"dc:contributor.department":["Electrical Engineering"],"dc:creator":["Modi, Manish Harsukh"],"dc:date.accessioned":["2014-03-14T21:34:29Z"],"dc:date.available":["2014-03-14T21:34:29Z","2009-04-25"],"dc:date.issued":["1990"],"dc:description.abstract":["A number of errors occur in digital systems operating in a harsh radiation environment. These errors are due to transient faults which may cause a temporary change in the state of the system without any permanent damage. These transient faults are referred to as Single Event Upsets (SEUs). Because of their random and non-recurring nature, such faults are very difficult to detect and hence are of source of great concern. This thesis examines the logical response of combinational logic circuits to SEUs. Time domain analyses of a large number of circuits attempts to determine the affect of an SEU on a flip-flop which might lay at the end of a chain of combinational logic gates. In this way, the concept of an upset window, as it pertains to different types of logic gates is introduced. The results of the simulations carried out on various blocks of combinational logic are discussed. A program called SUPER (SUsceptibility PrEdiction pRogram) is developed. SUPER predicts the probability of a circuit fault occurring given that a cosmic ray with certain energy characteristics impinges on an arbitrary point within an IC. IC. The input variables to SUPER include the radiation level, the duration of the radiation, the types of gates the radiation affects, the signal path, the type of voltage pulse that the radiation produces (rising or falling) and the time (with respect to the clock pulse) that the radiation is incident on the circuit. The output of SUPER consists of a prediction as to whether or not the incident radiation causes a change in the output of a flip-flop."],"dc:description.degree":["Master of Science"],"dc:format.medium":["BTD"],"dc:format.mimetype":["application/pdf"],"dc:identifier.other":["etd-04252009-040716"],"dc:identifier.uri":["http://hdl.handle.net/10919/42221"],"dc:language.iso":["en"],"dc:publisher":["Virginia Tech"],"dc:rights":["In Copyright"],"dc:rights.uri":["http://rightsstatements.org/vocab/InC/1.0/"],"dc:title":["Susceptibility evaluation of combinational logic in VLSI circuits"],"dc:type":["Thesis"],"dc:type.dcmitype":["Text"],"thesis:degree_discipline":["Electrical Engineering"],"thesis:degree_level":["masters"],"thesis:degree_name":["Master of Science"],"thesis:institution_name":["Virginia Polytechnic Institute and State University"]},"updated_at":"2026-07-22T22:20:41Z"}