{"id":{"repo_id":"vt","oai_identifier":"oai:vtechworks.lib.vt.edu:10919/42143"},"canonical_url":"https://search.dev.ndltd.org/etd/vt/oai:vtechworks.lib.vt.edu:10919/42143","repository":{"repo_id":"vt","name":"Virginia Tech","base_url":"https://vtechworks.lib.vt.edu/oai/request"},"display":{"title":"The use of VHDL in computer-aided support of life-cycle complete product design","abstract":"Successful competition in the computer systems industry depends on a firm's ability to bring profitable products to market. The success of a product is measured by its future worth to the company. Life-cycle complete design attempts to engineer products that provide maximum future worth. Many components contribute to the overall cost of developing a product. Designing merely to reduce the cost of the components that make up the system is insufficient. A product must be engineered in a manner that addresses all pertinent issues over its complete life cycle. This research examines the use of the VHSIC Hardware Description Language as a computer-aided engineering tool for life-cycle complete engineering. VHDL is traditionally used to model the functional behavior of digital systems. This thesis provides an overview of a life-cycle complete design process and describes the use of VHDL to support that process. A case study is presented to illustrate the use of VHDL for life-cycle complete modeling.","abstract_html":"Successful competition in the computer systems industry depends on a firm's ability to bring profitable products to market. The success of a product is measured by its future worth to the company. Life-cycle complete design attempts to engineer products that provide maximum future worth. Many components contribute to the overall cost of developing a product. Designing merely to reduce the cost of the components that make up the system is insufficient. A product must be engineered in a manner that addresses all pertinent issues over its complete life cycle. This research examines the use of the VHSIC Hardware Description Language as a computer-aided engineering tool for life-cycle complete engineering. VHDL is traditionally used to model the functional behavior of digital systems. This thesis provides an overview of a life-cycle complete design process and describes the use of VHDL to support that process. A case study is presented to illustrate the use of VHDL for life-cycle complete modeling.","abstract_has_math":false,"creators":["Hudson, Rhett Daniel"],"institution":"Virginia Tech","degree_name":"Master of Science","degree_level":"masters","degree_discipline":"Electrical Engineering","degree_department":"Electrical Engineering","school":null,"contributors":[],"advisors":[],"committee_chairs":["Midkiff, Scott F."],"committee_members":["Fabrycky, Wolter J.","Cyre, Walling R."],"year":1994,"date_issued":"1994-06-05","date_published":"1994-06-05","updated_at":"2026-07-22T22:18:50Z","subjects":[],"languages":["en"],"rights":["In Copyright"],"rights_urls":["http://rightsstatements.org/vocab/InC/1.0/"],"identifier_entries":[{"key":"dc:identifier.other","label":"Dc Identifier Other","values":["etd-04182009-041249"],"render_values":[{"text":"etd-04182009-041249","href":null,"code":true}]}]},"links":{"outbound_url":"http://hdl.handle.net/10919/42143","outbound_label":"Handle","outbound_source":"dc:identifier.uri"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor.committeechair","label":"Committee Chair","values":["Midkiff, Scott F."]},{"key":"dc:contributor.committeemember","label":"Committee Member","values":["Fabrycky, Wolter J.","Cyre, Walling R."]},{"key":"dc:contributor.department","label":"Department","values":["Electrical Engineering"]},{"key":"dc:creator","label":"Author","values":["Hudson, Rhett Daniel"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date.accessioned","label":"Dc Date Accessioned","values":["2014-03-14T21:34:06Z"]},{"key":"dc:date.available","label":"Dc Date Available","values":["2014-03-14T21:34:06Z","2009-04-18"]},{"key":"dc:date.issued","label":"Date","values":["1994-06-05"]},{"key":"dc:publisher","label":"Institution","values":["Virginia Tech"]},{"key":"dc:type","label":"Dc Type","values":["Thesis"]},{"key":"dc:type.dcmitype","label":"Dc Type Dcmitype","values":["Text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical Engineering"]},{"key":"thesis:degree_level","label":"Degree Level","values":["masters"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Master of Science"]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["Virginia Polytechnic Institute and State University"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language.iso","label":"Language (ISO)","values":["en"]},{"key":"dc:rights","label":"Dc Rights","values":["In Copyright"]},{"key":"dc:rights.uri","label":"Rights URI","values":["http://rightsstatements.org/vocab/InC/1.0/"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier.other","label":"Dc Identifier Other","values":["etd-04182009-041249"]},{"key":"dc:identifier.uri","label":"Identifier URI","values":["http://hdl.handle.net/10919/42143"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description.abstract","label":"Abstract","values":["Successful competition in the computer systems industry depends on a firm's ability to bring profitable products to market. The success of a product is measured by its future worth to the company. Life-cycle complete design attempts to engineer products that provide maximum future worth. Many components contribute to the overall cost of developing a product. Designing merely to reduce the cost of the components that make up the system is insufficient. A product must be engineered in a manner that addresses all pertinent issues over its complete life cycle. This research examines the use of the VHSIC Hardware Description Language as a computer-aided engineering tool for life-cycle complete engineering. VHDL is traditionally used to model the functional behavior of digital systems. This thesis provides an overview of a life-cycle complete design process and describes the use of VHDL to support that process. A case study is presented to illustrate the use of VHDL for life-cycle complete modeling."]},{"key":"dc:description.degree","label":"Dc Description Degree","values":["Master of Science"]},{"key":"dc:format.medium","label":"Dc Format Medium","values":["BTD"]},{"key":"dc:format.mimetype","label":"Dc Format Mimetype","values":["application/pdf"]},{"key":"dc:title","label":"Title","values":["The use of VHDL in computer-aided support of life-cycle complete product design"]}]}],"canonical_facts":{"dc:contributor.committeechair":["Midkiff, Scott F."],"dc:contributor.committeemember":["Fabrycky, Wolter J.","Cyre, Walling R."],"dc:contributor.department":["Electrical Engineering"],"dc:creator":["Hudson, Rhett Daniel"],"dc:date.accessioned":["2014-03-14T21:34:06Z"],"dc:date.available":["2014-03-14T21:34:06Z","2009-04-18"],"dc:date.issued":["1994-06-05"],"dc:description.abstract":["Successful competition in the computer systems industry depends on a firm's ability to bring profitable products to market. The success of a product is measured by its future worth to the company. Life-cycle complete design attempts to engineer products that provide maximum future worth. Many components contribute to the overall cost of developing a product. Designing merely to reduce the cost of the components that make up the system is insufficient. A product must be engineered in a manner that addresses all pertinent issues over its complete life cycle. This research examines the use of the VHSIC Hardware Description Language as a computer-aided engineering tool for life-cycle complete engineering. VHDL is traditionally used to model the functional behavior of digital systems. This thesis provides an overview of a life-cycle complete design process and describes the use of VHDL to support that process. A case study is presented to illustrate the use of VHDL for life-cycle complete modeling."],"dc:description.degree":["Master of Science"],"dc:format.medium":["BTD"],"dc:format.mimetype":["application/pdf"],"dc:identifier.other":["etd-04182009-041249"],"dc:identifier.uri":["http://hdl.handle.net/10919/42143"],"dc:language.iso":["en"],"dc:publisher":["Virginia Tech"],"dc:rights":["In Copyright"],"dc:rights.uri":["http://rightsstatements.org/vocab/InC/1.0/"],"dc:title":["The use of VHDL in computer-aided support of life-cycle complete product design"],"dc:type":["Thesis"],"dc:type.dcmitype":["Text"],"thesis:degree_discipline":["Electrical Engineering"],"thesis:degree_level":["masters"],"thesis:degree_name":["Master of Science"],"thesis:institution_name":["Virginia Polytechnic Institute and State University"]},"updated_at":"2026-07-22T22:18:50Z"}