Simulation of a binary phase shift keyed receiver with an IF correlator for position location

This thesis conducts a feasibility study of using a binary phase shift keyed receiver with an IF correlator in a position location application. The feasibility study is done using mathematical simulation. Traditionally the correlator, in a binary phase shift keyed receiver, is placed after the data demodulator. It correlates the incoming bitstream with a fixed reference bit sequence (synchronization header) to find the beginning of a data message. For position location applications this correlator is used to record the time of arrival of the signal at the receiver. These correlators can maintain the correlation peaks at best only to 1% of the bit period. At 4800 bits per second, this translates to an inherent range error of 625 meters. This thesis investigates the feasibility of using an additional correlator after the IF bandpass filter which will correlate the IF waveform sample by sample so as to maintain the correlation peaks to better than 1% of the bit period.

Name thesis:degree_name

Master of Science

Level thesis:degree_level

masters

Discipline thesis:degree_discipline

Electrical Engineering

Department dc:contributor.department

Electrical Engineering

Grantor dc:publisher

Virginia Tech

Year dc:date.issued

1993

Author dc:creator

• Thommana, John Vareed

Statement dc:rights

• In Copyright

Licence dc:rights.uri

• http://rightsstatements.org/vocab/InC/1.0/

Language dc:language.iso

en

Dc Identifier Other

etd-04082009-040445

OAI identifier oai:identifier

oai:vtechworks.lib.vt.edu:10919/41982