{"id":{"repo_id":"vt","oai_identifier":"oai:vtechworks.lib.vt.edu:10919/41343"},"canonical_url":"https://search.dev.ndltd.org/etd/vt/oai:vtechworks.lib.vt.edu:10919/41343","repository":{"repo_id":"vt","name":"Virginia Tech","base_url":"https://vtechworks.lib.vt.edu/oai/request"},"display":{"title":"Automatic verification of VHDL models","abstract":"Verification of a model describing a hardware system is very important for modeling and simulation purposes. It is necessary to ensure that the model accurately describes the hardware system. A scheme for the automatic verification of VHDL (VHSIC Hardware Description Language) models has been proposed. In the proposed scheme the specifications for the hardware system, i.e.,the timing constraints and relations between input and output signals are described by the designer in Modified Linear Time Temporal Logic,. which is an extension to traditional boolean logic and can describe timing relation between signals. A semantic similarity between temporal operators and VHDL timings and delays has been drawn and an algorithm for comparing the VHDL model and temporal specifications has been developed. Comparisons are made between the simulation results on the VHDL model and the temporal logic specifications and discrepancies are reported.","abstract_html":"Verification of a model describing a hardware system is very important for modeling and simulation purposes. It is necessary to ensure that the model accurately describes the hardware system. A scheme for the automatic verification of VHDL (VHSIC Hardware Description Language) models has been proposed. In the proposed scheme the specifications for the hardware system, i.e.,the timing constraints and relations between input and output signals are described by the designer in Modified Linear Time Temporal Logic,. which is an extension to traditional boolean logic and can describe timing relation between signals. A semantic similarity between temporal operators and VHDL timings and delays has been drawn and an algorithm for comparing the VHDL model and temporal specifications has been developed. Comparisons are made between the simulation results on the VHDL model and the temporal logic specifications and discrepancies are reported.","abstract_has_math":false,"creators":["Ardeishar, Raghu"],"institution":"Virginia Tech","degree_name":"Master of Science","degree_level":"masters","degree_discipline":"Electrical Engineering","degree_department":"Electrical Engineering","school":null,"contributors":[],"advisors":[],"committee_chairs":["Armstrong, James R.","Gray, Festus Gail"],"committee_members":["Cyre, Walling R."],"year":1990,"date_issued":"1990-07-07","date_published":"1990-07-07","updated_at":"2026-07-22T22:20:37Z","subjects":[],"languages":["en"],"rights":["In Copyright"],"rights_urls":["http://rightsstatements.org/vocab/InC/1.0/"],"identifier_entries":[{"key":"dc:identifier.other","label":"Dc Identifier Other","values":["etd-03032009-040338"],"render_values":[{"text":"etd-03032009-040338","href":null,"code":true}]}]},"links":{"outbound_url":"http://hdl.handle.net/10919/41343","outbound_label":"Handle","outbound_source":"dc:identifier.uri"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor.committeechair","label":"Committee Chair","values":["Armstrong, James R.","Gray, Festus Gail"]},{"key":"dc:contributor.committeemember","label":"Committee Member","values":["Cyre, Walling R."]},{"key":"dc:contributor.department","label":"Department","values":["Electrical Engineering"]},{"key":"dc:creator","label":"Author","values":["Ardeishar, Raghu"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date.accessioned","label":"Dc Date Accessioned","values":["2014-03-14T21:30:30Z"]},{"key":"dc:date.available","label":"Dc Date Available","values":["2014-03-14T21:30:30Z","2009-03-03"]},{"key":"dc:date.issued","label":"Date","values":["1990-07-07"]},{"key":"dc:publisher","label":"Institution","values":["Virginia Tech"]},{"key":"dc:type","label":"Dc Type","values":["Thesis"]},{"key":"dc:type.dcmitype","label":"Dc Type Dcmitype","values":["Text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical Engineering"]},{"key":"thesis:degree_level","label":"Degree Level","values":["masters"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Master of Science"]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["Virginia Polytechnic Institute and State University"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language.iso","label":"Language (ISO)","values":["en"]},{"key":"dc:rights","label":"Dc Rights","values":["In Copyright"]},{"key":"dc:rights.uri","label":"Rights URI","values":["http://rightsstatements.org/vocab/InC/1.0/"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier.other","label":"Dc Identifier Other","values":["etd-03032009-040338"]},{"key":"dc:identifier.uri","label":"Identifier URI","values":["http://hdl.handle.net/10919/41343"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description.abstract","label":"Abstract","values":["Verification of a model describing a hardware system is very important for modeling and simulation purposes. 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