A test generation system for behaviorally modeled digital circuits

This dissertation presents an approach to generating tests from a VHDL behavioral model. The tests can be used to thoroughly exercise the VHDL model and detect the faults in the equivalent gate level circuit of the model. The VHDL model is developed with the help of the Modeler's Assistant and represented as a Process Model Graph (PMG). A set of VHDL functions have been constructed to help develop VHDL models. Two algorithms are proposed to implement the test generation. <b>P-Algorithm</b> is used to generate tests at the process level. For each process a symbolic test set and the corresponding fixed valued test packages (FVTPs) are generated. Synthesis-related FVTP generation algorithms for the VHDL functions are derived to support the P-algorithm. <b>E-Algorithm</b> is employed to generate the entity level tests. The symbolic entity level tests are generated first and then the final fixed valued entity level tests are obtained by calculating the symbolic expressions. The Synopsys synthesis tools are used to get the equivalent gate level circuit of a VHDL model. The HILO fault grader is used to generate fault coverage. Several conversion programs have been developed to support the test evaluation.

Name thesis:degree_name

Ph. D.

Level thesis:degree_level

doctoral

Discipline thesis:degree_discipline

Electrical Engineering

Department dc:contributor.department

Electrical Engineering

Grantor dc:publisher

Virginia Tech

Year dc:date.issued

1996

Author dc:creator

• Li, Wencheng

Chair dc:contributor.committeechair

• Armstrong, James R.

Committee members dc:contributor.committeemember

• Balci, Osman
• Gray, F. Gail
• Cyre, Walling R.
• Athanas, P.M.

• VHDL models

Statement dc:rights

• In Copyright

Licence dc:rights.uri

• http://rightsstatements.org/vocab/InC/1.0/

Language dc:language.iso

en

Dc Identifier Other

etd-09232008-144806

OAI identifier oai:identifier

oai:vtechworks.lib.vt.edu:10919/39466