Planar Packaging and Electrical Characterization of High Temperature SiC Power Electronic Devices

This thesis examines the packaging of high-temperature SiC power electronic devices. Current-voltage measurements were conducted on as-received and packaged SiC power devices. The planar structure was introduced and developed as a substitution for traditional wire-bonding vertical structure. The planar structure was applied to a high temperature (>250oC) SiC power device. Based on the current-voltage (I-V) measurements, the packaging structures were improved, materials were selected, and processes were tightly controlled. This study applies two types of planar structures, the direct bond and the bump bond, to the high-temperature packaging of high-temperature SiC diode. A drop in the reverse breakdown voltage was discovered in the packaging using a direct bond. The root cause for the drop in the breakdown voltage was identified and corrective solutions were evaluated. A few effective methods were suggested for solving the breakdown issue. The forward I-V curve of the planar packaging using direct bond showed excellent results due to the excellent electrical and thermal properties of sintered nanosilver. The packaging using a bump bond as an improved structure was processed and proved to possess desirable forward and reverse I-V behavior. The cross-sections of both planar structures were inspected. High-temperature packaging materials, including nano-silver paste, high-lead solder ball and paste, adhesive epoxy, and encapsulant, were introduced and evaluated. The processes such as stencil printing, low-temperature sintering, solder reflowing, epoxy curing, sputtering deposition, electroplating, and patterning of direct-bond copper (DBC) were tightly controlled to ensure high-quality packaging with improved performance. Finally, the planar packaging of the high temperature power device was evaluated and summarized, and the future work was recommended.

Name thesis:degree_name

Master of Science

Level thesis:degree_level

masters

Discipline thesis:degree_discipline

Materials Science and Engineering

Department dc:contributor.department

Materials Science and Engineering

Grantor dc:publisher

Virginia Tech

Year dc:date.issued

2008

Author dc:creator

• Yue , Naili

Chairs dc:contributor.committeechair

• Lu, Guo-Quan
• Ngo, Khai D. T.

Committee members dc:contributor.committeemember

• Suchicital, Carlos T. A.
• Clark, David E.

• sintered nanoscale silver
• power electronic device
• planar structure
• high temperature
• solder bump

Statement dc:rights

• In Copyright

Licence dc:rights.uri

• http://rightsstatements.org/vocab/InC/1.0/

Language dc:language.iso

en

Dc Identifier Other

etd-12182008-231247

OAI identifier oai:identifier

oai:vtechworks.lib.vt.edu:10919/36278