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Virginia Tech

Overloaded Array Processing: System Analysis, Signal Extraction Techniques, and Time-delay Estimation

Abstract

dc:description.abstract

In airborne communication systems such as airborne cell-extender repeaters the receiver faces the challenge of demodulating the signal of interest (SOI) in the presence of excessive amounts of Co-Channel Interference (CCI) from a large number of sources. This results in the overloaded environment where the number of near-equal power co-channel interferers exceeds the number of antenna array elements. This thesis first analyzes the interference environment experienced by an airborne cellular repeater flying at high altitudes. Link budget analysis using a two-ray propagation model shows that the antenna array mounted on an airborne receiver has to recover the SOI out of hundreds of co-channel interfering signals. This necessitates use of complex overloaded array signal processing techniques. An extensive literature survey on narrowband signal extraction algorithms shows that joint detection schemes, coupled with antenna arrays, provide a solution for narrowband overloaded array problem where as traditional beamforming techniques fail. Simulation results in this thesis investigates three "promising" overloaded array processing algorithms, Multi-User Decision Feedback Equalizer (MU-DFE), Iterative Least Squares with Projection (ILSP), and Iterative Least Squares with Enumeration (ILSE). ILSE is a non-linear joint maximum-likelihood detector, is shown to demodulate many more signals than elements even when the users are closely spaced and the channel is blindly estimated. Multi-user time delay estimation is one of the most important aspects of channel estimation for overloaded array processing. The final chapter of the thesis proposes a low-complexity data-aided time-delay estimation structure for embedding in a Per Survivor Processing (PSP) trellis for overloaded array processing. An extensive analysis proves that the multi-user delay estimation is separable, which leads to the proposed multi-user algorithm that estimates the user delays with a bank of simple data-aided synchronization loops to reduce the complexity. This thesis shows simulation results for the single-user case where the low-complexity Delay Locked Loop (DLL) structure, working at a low oversampling rate of 2 samples per symbol, estimates and compensates for any integer or non-integer sample delay within ±Tsym(symbol period). Two extensions to this technique are proposed to provide efficient multi-user delay estimation. The first multi-user structure employs a bank of DLLs, which compensate for the timing offset of each user simultaneously. This multi-user algorithm is suitable for CDMA-type applications, where each user has a distinct PN-code with good auto- and cross-correlation properties. We show that for spreading gain of 31, the presence of an interpolator enables us to reduce the oversampling factor from 4 to 2 samples per chip. Thus, the requirements of the A/D converter are relaxed without sacrificing system performance. Furthermore, we show that the proposed scheme meets the requirements of multi-user interference cancellation techniques for residual worst-case timing errors, i.e., residual timing error < 0.2 Tc, as reported in [200]. Finally, the thesis recommends a similar multi-user structure for narrowband TDMA-type system, which is based on bank of DLLs with whitening pre-filters at the front end of each branch.

Degree

thesis:*
Name thesis:degree_name
Master of Science
Level thesis:degree_level
masters
Discipline thesis:degree_discipline
Electrical and Computer Engineering
Department dc:contributor.department
Electrical and Computer Engineering
Grantor dc:publisher
Virginia Tech
Year dc:date.issued
2000

Author and committee

dc:creator, dc:contributor.*
Author dc:creator
  • Bayram, Saffet
Chair dc:contributor.committeechair
  • Reed, Jeffrey H.
Committee members dc:contributor.committeemember
  • Boyle, Robert J.
  • Woerner, Brian D.

Subjects

dc:subject × 4

Rights

dc:rights
Statement dc:rights
  • In Copyright

Identifiers

dc:identifier.*
Dc Identifier Other
etd-12102000-183343
OAI identifier oai:identifier
oai:vtechworks.lib.vt.edu:10919/36039

Chain of custody

source
Harvested from
Virginia Tech
Base URL
vtechworks.lib.vt.edu/oai/request
Last updated
2026-07-22
Source record
OAI-PMH GetRecord
citation

Bayram, Saffet. Overloaded Array Processing: System Analysis, Signal Extraction Techniques, and Time-delay Estimation. masters thesis, Virginia Tech, 2000. http://hdl.handle.net/10919/36039