{"id":{"repo_id":"vt","oai_identifier":"oai:vtechworks.lib.vt.edu:10919/35863"},"canonical_url":"https://search.dev.ndltd.org/etd/vt/oai:vtechworks.lib.vt.edu:10919/35863","repository":{"repo_id":"vt","name":"Virginia Tech","base_url":"https://vtechworks.lib.vt.edu/oai/request"},"display":{"title":"Fabrication of Three-Dimensionally Independent Microchannels Using a Single Mask Aimed at On-Chip Microprocessor Cooling","abstract":"A novel fabrication process is presented which allows for three-dimensionally independent features to be etched in silicon using SF6 gas in a deep reactive ion etcher (DRIE) after a single etch step. The mechanism allowing for different feature depths and widths to be produced over a wafer is reactive ion etch lag, where etch rate scales with the exposed feature size in the mask. A modified Langmuir model has been developed relating the geometry of the exposed areas in a specific mask pattern as well as the etch duration to the final depth and width of a channel that is produced after isotropic silicon etching. This fabrication process is tailored for microfluidic network design, but the capabilities of the process can be applied elsewhere. A characterization of an Alcatel DRIE tool is also presented in order to enhance RIE lag by varying etch process parameters, increasing the variety of channel sizes that can be fabricated. High values of flow rate, coil power, and pressure were found to produce this effect. The capability of the modeled process for creating a microchip cooling device for high-heat flux applications was also investigated. Using meander channels, heat flux in excess of 100W/cm2 were cooled using 750µL/s flow rate of water through the chip. This single-mask process reduces risk of damage to the chip and provides the capability to cool high-heat-flux microprocessors for the next 10 years, and for an even longer time once the geometry of the channels is optimized.","abstract_html":"A novel fabrication process is presented which allows for three-dimensionally independent features to be etched in silicon using SF6 gas in a deep reactive ion etcher (DRIE) after a single etch step. The mechanism allowing for different feature depths and widths to be produced over a wafer is reactive ion etch lag, where etch rate scales with the exposed feature size in the mask. A modified Langmuir model has been developed relating the geometry of the exposed areas in a specific mask pattern as well as the etch duration to the final depth and width of a channel that is produced after isotropic silicon etching. This fabrication process is tailored for microfluidic network design, but the capabilities of the process can be applied elsewhere. A characterization of an Alcatel DRIE tool is also presented in order to enhance RIE lag by varying etch process parameters, increasing the variety of channel sizes that can be fabricated. High values of flow rate, coil power, and pressure were found to produce this effect. The capability of the modeled process for creating a microchip cooling device for high-heat flux applications was also investigated. Using meander channels, heat flux in excess of 100W/cm2 were cooled using 750µL/s flow rate of water through the chip. This single-mask process reduces risk of damage to the chip and provides the capability to cool high-heat-flux microprocessors for the next 10 years, and for an even longer time once the geometry of the channels is optimized.","abstract_has_math":false,"creators":["Gantz, Kevin Francis"],"institution":"Virginia Tech","degree_name":"Master of Science","degree_level":"masters","degree_discipline":"Mechanical Engineering","degree_department":"Mechanical Engineering","school":null,"contributors":[],"advisors":[],"committee_chairs":["Agah, Masoud"],"committee_members":["Huxtable, Scott T.","Raman, Sanjay","Nazhandali, Leyla"],"year":2007,"date_issued":"2007-11-28","date_published":"2007-11-28","updated_at":"2026-07-22T22:20:38Z","subjects":["nonlinear regression","isotropic etching","chip cooling","CMOS compatible","RIE lag","microfluidics"],"languages":[],"rights":["In Copyright"],"rights_urls":["http://rightsstatements.org/vocab/InC/1.0/"],"identifier_entries":[{"key":"dc:identifier.other","label":"Dc Identifier Other","values":["etd-11302007-113409"],"render_values":[{"text":"etd-11302007-113409","href":null,"code":true}]}]},"links":{"outbound_url":"http://hdl.handle.net/10919/35863","outbound_label":"Handle","outbound_source":"dc:identifier.uri"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor.committeechair","label":"Committee Chair","values":["Agah, Masoud"]},{"key":"dc:contributor.committeemember","label":"Committee Member","values":["Huxtable, Scott T.","Raman, Sanjay","Nazhandali, Leyla"]},{"key":"dc:contributor.department","label":"Department","values":["Mechanical Engineering"]},{"key":"dc:creator","label":"Author","values":["Gantz, Kevin Francis"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date.accessioned","label":"Dc Date Accessioned","values":["2014-03-14T20:48:33Z"]},{"key":"dc:date.available","label":"Dc Date Available","values":["2014-03-14T20:48:33Z","2010-12-22"]},{"key":"dc:date.issued","label":"Date","values":["2007-11-28"]},{"key":"dc:publisher","label":"Institution","values":["Virginia Tech"]},{"key":"dc:type","label":"Dc Type","values":["Thesis"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Mechanical Engineering"]},{"key":"thesis:degree_level","label":"Degree Level","values":["masters"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Master of Science"]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["Virginia Polytechnic Institute and State University"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["nonlinear regression","isotropic etching","chip cooling","CMOS compatible","RIE lag","microfluidics"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:rights","label":"Dc Rights","values":["In Copyright"]},{"key":"dc:rights.uri","label":"Rights URI","values":["http://rightsstatements.org/vocab/InC/1.0/"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier.other","label":"Dc Identifier Other","values":["etd-11302007-113409"]},{"key":"dc:identifier.uri","label":"Identifier URI","values":["http://hdl.handle.net/10919/35863"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description.abstract","label":"Abstract","values":["A novel fabrication process is presented which allows for three-dimensionally independent features to be etched in silicon using SF6 gas in a deep reactive ion etcher (DRIE) after a single etch step. The mechanism allowing for different feature depths and widths to be produced over a wafer is reactive ion etch lag, where etch rate scales with the exposed feature size in the mask. A modified Langmuir model has been developed relating the geometry of the exposed areas in a specific mask pattern as well as the etch duration to the final depth and width of a channel that is produced after isotropic silicon etching. This fabrication process is tailored for microfluidic network design, but the capabilities of the process can be applied elsewhere. A characterization of an Alcatel DRIE tool is also presented in order to enhance RIE lag by varying etch process parameters, increasing the variety of channel sizes that can be fabricated. High values of flow rate, coil power, and pressure were found to produce this effect. The capability of the modeled process for creating a microchip cooling device for high-heat flux applications was also investigated. Using meander channels, heat flux in excess of 100W/cm2 were cooled using 750µL/s flow rate of water through the chip. This single-mask process reduces risk of damage to the chip and provides the capability to cool high-heat-flux microprocessors for the next 10 years, and for an even longer time once the geometry of the channels is optimized."]},{"key":"dc:description.degree","label":"Dc Description Degree","values":["Master of Science"]},{"key":"dc:title","label":"Title","values":["Fabrication of Three-Dimensionally Independent Microchannels Using a Single Mask Aimed at On-Chip Microprocessor Cooling"]}]}],"canonical_facts":{"dc:contributor.committeechair":["Agah, Masoud"],"dc:contributor.committeemember":["Huxtable, Scott T.","Raman, Sanjay","Nazhandali, Leyla"],"dc:contributor.department":["Mechanical Engineering"],"dc:creator":["Gantz, Kevin Francis"],"dc:date.accessioned":["2014-03-14T20:48:33Z"],"dc:date.available":["2014-03-14T20:48:33Z","2010-12-22"],"dc:date.issued":["2007-11-28"],"dc:description.abstract":["A novel fabrication process is presented which allows for three-dimensionally independent features to be etched in silicon using SF6 gas in a deep reactive ion etcher (DRIE) after a single etch step. The mechanism allowing for different feature depths and widths to be produced over a wafer is reactive ion etch lag, where etch rate scales with the exposed feature size in the mask. A modified Langmuir model has been developed relating the geometry of the exposed areas in a specific mask pattern as well as the etch duration to the final depth and width of a channel that is produced after isotropic silicon etching. This fabrication process is tailored for microfluidic network design, but the capabilities of the process can be applied elsewhere. A characterization of an Alcatel DRIE tool is also presented in order to enhance RIE lag by varying etch process parameters, increasing the variety of channel sizes that can be fabricated. High values of flow rate, coil power, and pressure were found to produce this effect. The capability of the modeled process for creating a microchip cooling device for high-heat flux applications was also investigated. Using meander channels, heat flux in excess of 100W/cm2 were cooled using 750µL/s flow rate of water through the chip. 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