A Scaleable FIR Filter Implementation Using 32-bit Floating-Point Complex Arithmetic on a FPGA Base Custom Computing Platform

This thesis presents a linear phase finite impulse response filter implementation developed on a custom computing platform called WILDFORCE. The work has been motivated by ways to off-load intensive computing tasks to hardware for indoor communications channel modeling. The design entails complex convolution filters with customized lengths that can support channel impulse response profiles generated by SIRCIM. The paper details the partitioning for a fully pipelined convolution algorithm onto field programmable gate arrays through VHDL synthesis. Using WILDFORCE, the filter can achieve calculations at 160 MFLOPs/s.

Name thesis:degree_name

Master of Science

Level thesis:degree_level

masters

Discipline thesis:degree_discipline

Electrical Engineering

Department dc:contributor.department

Electrical Engineering

Grantor dc:publisher

Virginia Tech

Year dc:date.issued

1998

Author dc:creator

• Walters, Allison L.

Chair dc:contributor.committeechair

• Athanas, Peter M.

Committee members dc:contributor.committeemember

• Jones, Mark T.
• Davis, Nathaniel J. IV

• reconfigurable computing
• digital signal processing
• FIR filters

Statement dc:rights

• In Copyright

Licence dc:rights.uri

• http://rightsstatements.org/vocab/InC/1.0/

Dc Identifier Other

etd-11198-212219

OAI identifier oai:identifier

oai:vtechworks.lib.vt.edu:10919/35765