{"id":{"repo_id":"vt","oai_identifier":"oai:vtechworks.lib.vt.edu:10919/34487"},"canonical_url":"https://search.dev.ndltd.org/etd/vt/oai:vtechworks.lib.vt.edu:10919/34487","repository":{"repo_id":"vt","name":"Virginia Tech","base_url":"https://vtechworks.lib.vt.edu/oai/request"},"display":{"title":"A Multi-Language Goal-Tree Based Functional Test Planning System","abstract":"Test plans are used to guide, organize and document the testing activities during hardware design process. Manual test planning and configuration is known to be labor intensive, time consuming and error prone. It is desirable to develop efficient approaches to model testing and to develop test tools to automate test-planning activities. With the emergence of new hardware design paradigms, there is a need to develop more specialized description languages. However, adopting a new language for hardware-based designs involves adapting the existing design and verification tool suite for the new language. This is a very time consuming and capital intensive process. To ease the adoption of new description languages, it is desirable to develop multi-language support methodologies for design and test tools. This thesis addresses a subset of these problems. It presents a goal-tree based test methodology which is very effective for functional testing of hardware models in multiple application domains. Then it describes an approach for achieving a high degree of language independence using ideas of data abstraction. It also presents an automated test-planning tool called the \"Goal Tree System (GTS)\", which provides an implementation of goal tree methodology and multi-language support ideas. We demonstrate the use of this tool by testing models developed in VHDL and SystemC. We also present the design aspects of the Goal Tree System, which enable it to work across multiple platforms and with multiple simulators.","abstract_html":"Test plans are used to guide, organize and document the testing activities during hardware design process. Manual test planning and configuration is known to be labor intensive, time consuming and error prone. It is desirable to develop efficient approaches to model testing and to develop test tools to automate test-planning activities. With the emergence of new hardware design paradigms, there is a need to develop more specialized description languages. However, adopting a new language for hardware-based designs involves adapting the existing design and verification tool suite for the new language. This is a very time consuming and capital intensive process. To ease the adoption of new description languages, it is desirable to develop multi-language support methodologies for design and test tools. This thesis addresses a subset of these problems. It presents a goal-tree based test methodology which is very effective for functional testing of hardware models in multiple application domains. Then it describes an approach for achieving a high degree of language independence using ideas of data abstraction. It also presents an automated test-planning tool called the "Goal Tree System (GTS)", which provides an implementation of goal tree methodology and multi-language support ideas. We demonstrate the use of this tool by testing models developed in VHDL and SystemC. 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