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Virginia Tech

Design of a Power-aware Dataflow Processor Architecture

Abstract

dc:description.abstract

In a sensor monitoring embedded computing environment, the data from a sensor is an event that triggers the execution of an application. A sensor node consists of multiple sensors and a general purpose processor that handles the multiple events by deploying an event-driven software model. The software overheads of the general purpose processors results in energy inefficiency. What is needed is a class of special purpose processing elements which are more energy efficient for the purpose of computation. In the past, special purpose microcontrollers have been designed which are energy efficient for the targeted application space. However, reuse of the same design techniques is not feasible for other application domains. Therefore, this thesis presents a power-aware dataflow processor architecture targeted for the electronic textile computing space. The processor architecture has no instructions, and handles multiple events inherently without deploying software methods. This thesis also shows that the power-aware implementation reduces the overall static power consumption.

Degree

thesis:*
Name thesis:degree_name
Master of Science
Level thesis:degree_level
masters
Discipline thesis:degree_discipline
Electrical and Computer Engineering
Department dc:contributor.department
Electrical and Computer Engineering
Grantor dc:publisher
Virginia Tech
Year dc:date.issued
2010

Author and committee

dc:creator, dc:contributor.*
Author dc:creator
  • Narayanaswamy, Ramya Priyadharshini
Chairs dc:contributor.committeechair
  • Jones, Mark T.
  • Martin, Thomas L.
Committee member dc:contributor.committeemember
  • Plassmann, Paul E.

Subjects

dc:subject × 4

Rights

dc:rights
Statement dc:rights
  • In Copyright

Identifiers

dc:identifier.*
Dc Identifier Other
etd-07262010-183257
OAI identifier oai:identifier
oai:vtechworks.lib.vt.edu:10919/34192

Chain of custody

source
Harvested from
Virginia Tech
Base URL
vtechworks.lib.vt.edu/oai/request
Last updated
2026-07-22
Source record
OAI-PMH GetRecord
citation

Narayanaswamy, Ramya Priyadharshini. Design of a Power-aware Dataflow Processor Architecture. masters thesis, Virginia Tech, 2010. http://hdl.handle.net/10919/34192