{"id":{"repo_id":"vt","oai_identifier":"oai:vtechworks.lib.vt.edu:10919/33649"},"canonical_url":"https://search.dev.ndltd.org/etd/vt/oai:vtechworks.lib.vt.edu:10919/33649","repository":{"repo_id":"vt","name":"Virginia Tech","base_url":"https://vtechworks.lib.vt.edu/oai/request"},"display":{"title":"An FPGA-based Run-time Reconfigurable 2-D Discrete Wavelet Transform Core","abstract":"FPGAs provide an ideal template for run-time reconfigurable (RTR) designs. Only recently have RTR enabling design tools that bypass the traditional synthesis and bitstream generation process for FPGAs become available. The JBits tool suite is an environment that provides support for RTR designs on Xilinx Virtex and 4K devices. This research provides a comprehensive design process description of a two-dimensional discrete wavelet transform (DWT) core using the JBits run-time reconfigurable FPGA design tool suite. Several aspects of the design process are discussed, including implementation, simulation, debugging, and hardware interfacing to a reconfigurable computing platform. The DWT lends itself to a straightforward implementation in hardware, requiring relatively simple logic for control and address generation circuitry. Through the application of RTR techniques to the DWT, this research attempts to exploit certain advantages that are unobtainable with static implementations. Performance results of the DWT core are presented, including speed of operation, resource consumption, and reconfiguration overhead times.","abstract_html":"FPGAs provide an ideal template for run-time reconfigurable (RTR) designs. Only recently have RTR enabling design tools that bypass the traditional synthesis and bitstream generation process for FPGAs become available. The JBits tool suite is an environment that provides support for RTR designs on Xilinx Virtex and 4K devices. This research provides a comprehensive design process description of a two-dimensional discrete wavelet transform (DWT) core using the JBits run-time reconfigurable FPGA design tool suite. Several aspects of the design process are discussed, including implementation, simulation, debugging, and hardware interfacing to a reconfigurable computing platform. The DWT lends itself to a straightforward implementation in hardware, requiring relatively simple logic for control and address generation circuitry. Through the application of RTR techniques to the DWT, this research attempts to exploit certain advantages that are unobtainable with static implementations. Performance results of the DWT core are presented, including speed of operation, resource consumption, and reconfiguration overhead times.","abstract_has_math":false,"creators":["Ballagh, Jonathan Bartlett"],"institution":"Virginia Tech","degree_name":"Master of Science","degree_level":"masters","degree_discipline":"Electrical and Computer Engineering","degree_department":"Electrical and Computer Engineering","school":null,"contributors":[],"advisors":[],"committee_chairs":["Athanas, Peter M."],"committee_members":["Jones, Mark T.","Patterson, Cameron D.","Bell, Amy E."],"year":2001,"date_issued":"2001-06-15","date_published":"2001-06-15","updated_at":"2026-07-22T22:20:26Z","subjects":["JBits","Wavelets","Field programmable gate arrays","Reconfiguration"],"languages":[],"rights":["In Copyright"],"rights_urls":["http://rightsstatements.org/vocab/InC/1.0/"],"identifier_entries":[{"key":"dc:identifier.other","label":"Dc Identifier Other","values":["etd-06192001-112019"],"render_values":[{"text":"etd-06192001-112019","href":null,"code":true}]}]},"links":{"outbound_url":"http://hdl.handle.net/10919/33649","outbound_label":"Handle","outbound_source":"dc:identifier.uri"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor.committeechair","label":"Committee Chair","values":["Athanas, Peter M."]},{"key":"dc:contributor.committeemember","label":"Committee Member","values":["Jones, Mark T.","Patterson, Cameron D.","Bell, Amy E."]},{"key":"dc:contributor.department","label":"Department","values":["Electrical and Computer Engineering"]},{"key":"dc:creator","label":"Author","values":["Ballagh, Jonathan Bartlett"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date.accessioned","label":"Dc Date Accessioned","values":["2014-03-14T20:40:14Z"]},{"key":"dc:date.available","label":"Dc Date Available","values":["2014-03-14T20:40:14Z","2002-06-20"]},{"key":"dc:date.issued","label":"Date","values":["2001-06-15"]},{"key":"dc:publisher","label":"Institution","values":["Virginia Tech"]},{"key":"dc:type","label":"Dc Type","values":["Thesis"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical and Computer Engineering"]},{"key":"thesis:degree_level","label":"Degree Level","values":["masters"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Master of Science"]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["Virginia Polytechnic Institute and State University"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["JBits","Wavelets","Field programmable gate arrays","Reconfiguration"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:rights","label":"Dc Rights","values":["In Copyright"]},{"key":"dc:rights.uri","label":"Rights URI","values":["http://rightsstatements.org/vocab/InC/1.0/"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier.other","label":"Dc Identifier Other","values":["etd-06192001-112019"]},{"key":"dc:identifier.uri","label":"Identifier URI","values":["http://hdl.handle.net/10919/33649"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description.abstract","label":"Abstract","values":["FPGAs provide an ideal template for run-time reconfigurable (RTR) designs. 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Performance results of the DWT core are presented, including speed of operation, resource consumption, and reconfiguration overhead times."]},{"key":"dc:description.degree","label":"Dc Description Degree","values":["Master of Science"]},{"key":"dc:title","label":"Title","values":["An FPGA-based Run-time Reconfigurable 2-D Discrete Wavelet Transform Core"]}]}],"canonical_facts":{"dc:contributor.committeechair":["Athanas, Peter M."],"dc:contributor.committeemember":["Jones, Mark T.","Patterson, Cameron D.","Bell, Amy E."],"dc:contributor.department":["Electrical and Computer Engineering"],"dc:creator":["Ballagh, Jonathan Bartlett"],"dc:date.accessioned":["2014-03-14T20:40:14Z"],"dc:date.available":["2014-03-14T20:40:14Z","2002-06-20"],"dc:date.issued":["2001-06-15"],"dc:description.abstract":["FPGAs provide an ideal template for run-time reconfigurable (RTR) designs. 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