{"id":{"repo_id":"vt","oai_identifier":"oai:vtechworks.lib.vt.edu:10919/31458"},"canonical_url":"https://search.dev.ndltd.org/etd/vt/oai:vtechworks.lib.vt.edu:10919/31458","repository":{"repo_id":"vt","name":"Virginia Tech","base_url":"https://vtechworks.lib.vt.edu/oai/request"},"display":{"title":"A Low-Power Design of Motion Estimation Blocks for Low Bit-Rate Wireless Video Communications","abstract":"Motion estimation and motion compensation comprise one of the most important compression methods for video communications. We propose a low-power design of a motion estimation block for a low bit-rate video codec standard H.263. Since the motion estimation is computationally intensive to result in large power consumption, a low-power design is essential for portable or mobile systems. Our block employs the Four-Step Search (4SS) method as its primary algorithm. The design and the algorithm have been optimized to provide adequate results for low-quality video at low-power consumption. The model is developed in VHDL and synthesized using a 0.35 um CMOS library. Power consumption of both gate-level circuits and memory-accesses have been considered. Gate-level simulation shows the proposed design offers a 38% power reduction over a \"baseline\" implementation of a 4SS model and a 60% power reduction over a baseline Three-Step Search (TSS) model. Power savings through reduction of memory access is 26% over the TSS model and 32% over the 4SS model. The total power consumption of the proposed motion estimation block ranges from 7 - 9 mW and is dependent on the type of video being motion estimated.","abstract_html":"Motion estimation and motion compensation comprise one of the most important compression methods for video communications. We propose a low-power design of a motion estimation block for a low bit-rate video codec standard H.263. Since the motion estimation is computationally intensive to result in large power consumption, a low-power design is essential for portable or mobile systems. Our block employs the Four-Step Search (4SS) method as its primary algorithm. The design and the algorithm have been optimized to provide adequate results for low-quality video at low-power consumption. The model is developed in VHDL and synthesized using a 0.35 um CMOS library. Power consumption of both gate-level circuits and memory-accesses have been considered. Gate-level simulation shows the proposed design offers a 38% power reduction over a "baseline" implementation of a 4SS model and a 60% power reduction over a baseline Three-Step Search (TSS) model. Power savings through reduction of memory access is 26% over the TSS model and 32% over the 4SS model. The total power consumption of the proposed motion estimation block ranges from 7 - 9 mW and is dependent on the type of video being motion estimated.","abstract_has_math":false,"creators":["Richmond II, Richard Steven"],"institution":"Virginia Tech","degree_name":"Master of Science","degree_level":"masters","degree_discipline":"Electrical and Computer Engineering","degree_department":"Electrical and Computer Engineering","school":null,"contributors":[],"advisors":[],"committee_chairs":["Ha, Dong Sam"],"committee_members":["Reed, Jeffrey H.","Armstrong, James R."],"year":2001,"date_issued":"2001-03-13","date_published":"2001-03-13","updated_at":"2026-07-24T05:56:46Z","subjects":["Four-step search","Low power","Motion estimation","H.263"],"languages":[],"rights":["In Copyright"],"rights_urls":["http://rightsstatements.org/vocab/InC/1.0/"],"identifier_entries":[{"key":"dc:identifier.other","label":"Dc Identifier Other","values":["etd-03132001-140635"],"render_values":[{"text":"etd-03132001-140635","href":null,"code":true}]}]},"links":{"outbound_url":"http://hdl.handle.net/10919/31458","outbound_label":"Handle","outbound_source":"dc:identifier.uri"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor.committeechair","label":"Committee Chair","values":["Ha, Dong Sam"]},{"key":"dc:contributor.committeemember","label":"Committee Member","values":["Reed, Jeffrey H.","Armstrong, James R."]},{"key":"dc:contributor.department","label":"Department","values":["Electrical and Computer Engineering"]},{"key":"dc:creator","label":"Author","values":["Richmond II, Richard Steven"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date.accessioned","label":"Dc Date Accessioned","values":["2014-03-14T20:32:36Z"]},{"key":"dc:date.available","label":"Dc Date Available","values":["2014-03-14T20:32:36Z","2002-03-14"]},{"key":"dc:date.issued","label":"Date","values":["2001-03-13"]},{"key":"dc:publisher","label":"Institution","values":["Virginia Tech"]},{"key":"dc:type","label":"Dc Type","values":["Thesis"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical and Computer Engineering"]},{"key":"thesis:degree_level","label":"Degree Level","values":["masters"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Master of Science"]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["Virginia Polytechnic Institute and State University"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Four-step search","Low power","Motion estimation","H.263"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:rights","label":"Dc Rights","values":["In Copyright"]},{"key":"dc:rights.uri","label":"Rights URI","values":["http://rightsstatements.org/vocab/InC/1.0/"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier.other","label":"Dc Identifier Other","values":["etd-03132001-140635"]},{"key":"dc:identifier.uri","label":"Identifier URI","values":["http://hdl.handle.net/10919/31458"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description.abstract","label":"Abstract","values":["Motion estimation and motion compensation comprise one of the most important compression methods for video communications. We propose a low-power design of a motion estimation block for a low bit-rate video codec standard H.263. Since the motion estimation is computationally intensive to result in large power consumption, a low-power design is essential for portable or mobile systems. Our block employs the Four-Step Search (4SS) method as its primary algorithm. The design and the algorithm have been optimized to provide adequate results for low-quality video at low-power consumption. The model is developed in VHDL and synthesized using a 0.35 um CMOS library. Power consumption of both gate-level circuits and memory-accesses have been considered. Gate-level simulation shows the proposed design offers a 38% power reduction over a \"baseline\" implementation of a 4SS model and a 60% power reduction over a baseline Three-Step Search (TSS) model. Power savings through reduction of memory access is 26% over the TSS model and 32% over the 4SS model. The total power consumption of the proposed motion estimation block ranges from 7 - 9 mW and is dependent on the type of video being motion estimated."]},{"key":"dc:description.degree","label":"Dc Description Degree","values":["Master of Science"]},{"key":"dc:title","label":"Title","values":["A Low-Power Design of Motion Estimation Blocks for Low Bit-Rate Wireless Video Communications"]}]}],"canonical_facts":{"dc:contributor.committeechair":["Ha, Dong Sam"],"dc:contributor.committeemember":["Reed, Jeffrey H.","Armstrong, James R."],"dc:contributor.department":["Electrical and Computer Engineering"],"dc:creator":["Richmond II, Richard Steven"],"dc:date.accessioned":["2014-03-14T20:32:36Z"],"dc:date.available":["2014-03-14T20:32:36Z","2002-03-14"],"dc:date.issued":["2001-03-13"],"dc:description.abstract":["Motion estimation and motion compensation comprise one of the most important compression methods for video communications. We propose a low-power design of a motion estimation block for a low bit-rate video codec standard H.263. Since the motion estimation is computationally intensive to result in large power consumption, a low-power design is essential for portable or mobile systems. Our block employs the Four-Step Search (4SS) method as its primary algorithm. The design and the algorithm have been optimized to provide adequate results for low-quality video at low-power consumption. The model is developed in VHDL and synthesized using a 0.35 um CMOS library. Power consumption of both gate-level circuits and memory-accesses have been considered. Gate-level simulation shows the proposed design offers a 38% power reduction over a \"baseline\" implementation of a 4SS model and a 60% power reduction over a baseline Three-Step Search (TSS) model. Power savings through reduction of memory access is 26% over the TSS model and 32% over the 4SS model. The total power consumption of the proposed motion estimation block ranges from 7 - 9 mW and is dependent on the type of video being motion estimated."],"dc:description.degree":["Master of Science"],"dc:identifier.other":["etd-03132001-140635"],"dc:identifier.uri":["http://hdl.handle.net/10919/31458"],"dc:publisher":["Virginia Tech"],"dc:rights":["In Copyright"],"dc:rights.uri":["http://rightsstatements.org/vocab/InC/1.0/"],"dc:subject":["Four-step search","Low power","Motion estimation","H.263"],"dc:title":["A Low-Power Design of Motion Estimation Blocks for Low Bit-Rate Wireless Video Communications"],"dc:type":["Thesis"],"thesis:degree_discipline":["Electrical and Computer Engineering"],"thesis:degree_level":["masters"],"thesis:degree_name":["Master of Science"],"thesis:institution_name":["Virginia Polytechnic Institute and State University"]},"updated_at":"2026-07-24T05:56:46Z"}