Integrated Electrical and Thermal Modeling, Analysis and Design for IPEM

The goal of this dissertation is to present a systematic approach to integrating the multidisciplinary design process in power electronics through the integration of existing CAD tools, multidisciplinary modeling and system optimization. Two major benefits are expected from the utilization of the proposed integrated design methodology. Firstly, it will significantly speed up the design process and will eliminate errors resulting from repeated manual data entry and information exchange. Secondly, the integrated design optimization will result in better utilization of materials and components. In order to understand the basic relationship between electrical and thermal phenomena, the self-heating effect of a simple copper conductor is modeled analytically. Based on these models, a guideline for copper trace design is proposed. The next step towards developing an integrated design methodology is to create threedimensional solid-body-based models that characterize the electrical, thermal and mechanical properties. The electrical model of an integrated power electronics module (IPEM), including parasitic parameters, is developed and experimentally verified with impedance measurements. Together with the thermal model, it lays the foundation for the integrated electrical and thermal analysis and design. The software integration framework is presented along with the software tools chosen for this study, which include Saber for electrical circuit simulation, Maxwell Q3D Extractor for parameter extraction, and I-DEAS for geometry and thermal modeling. Each of these software tools is controlled via its own macro language files. iSIGHT is then used to interface with these tools in order to achieve software integration. The DC-DC IPEM layout design is investigated and improved upon by using the integrated design methodology. Several examples of parametric study are presented. The first example shows the tradeoff between electrical and thermal performance for different ceramic layer thicknesses of module substrate. The next example looks at the commonmode noise problem that exists in different direct-bonded copper (DBC) layouts.

Name thesis:degree_name

Ph. D.

Level thesis:degree_level

doctoral

Discipline thesis:degree_discipline

Electrical and Computer Engineering

Department dc:contributor.department

Electrical and Computer Engineering

Grantor dc:publisher

Virginia Tech

Year dc:date.issued

2004

Author dc:creator

• Chen, Zhou

Chair dc:contributor.committeechair

• Boroyevich, Dushan

Committee members dc:contributor.committeemember

• Bohn, Jan Helge
• Lee, Fred C.
• Odendaal, Willem Gerhardus
• Liu, Yilu

• system integration
• integrated electrical and thermal analysis
• power electronics module
• parasitic parameter extraction

Statement dc:rights

• In Copyright

Licence dc:rights.uri

• http://rightsstatements.org/vocab/InC/1.0/

Dc Identifier Other

etd-12302004-123049

OAI identifier oai:identifier

oai:vtechworks.lib.vt.edu:10919/30281