Abstract
dc:description.abstractThe ability of some configurable logic devices to modify their hardware during operation has long held great potential to increase performance and reduce device cost. However, despite many research projects and a decade of research, the dynamic reconfiguration of Field Programmable Gate Arrays (FPGAs) is still very much an art practiced by few. Previous attempts to automate the many low-level details that complicate Run-Time Reconfigurable (RTR) application development suffer severe limitations. This dissertation describes a comprehensive approach to dynamic hardware development, providing a designer with appropriate models for computation, communication, and reconfiguration integrated with a high-level design environment. In this way, many manual and time consuming tasks associated with partial reconfiguration are hidden, permitting a designer to focus instead on a design's behavior. This design and implementation environment has been validated on a variety of relevant applications, quantifying the effects of high-level design.
Degree
thesis:*- Name thesis:degree_name
- Ph. D.
- Level thesis:degree_level
- doctoral
- Discipline thesis:degree_discipline
- Electrical and Computer Engineering
- Department dc:contributor.department
- Electrical and Computer Engineering
- Grantor dc:publisher
- Virginia Tech
- Year dc:date.issued
- 2008
Author and committee
dc:creator, dc:contributor.*- Author dc:creator
-
- Craven, Stephen Douglas
- Chair dc:contributor.committeechair
-
- Athanas, Peter M.
- Committee members dc:contributor.committeemember
-
- Schaumont, Patrick R.
- Patterson, Cameron D.
- Bohner, Shawn A.
- Brown, Gary S.
Subjects
dc:subject × 4Rights
dc:rights- Statement dc:rights
-
- In Copyright
- Licence dc:rights.uri
Identifiers
dc:identifier.*- Dc Identifier Other
- etd-05152008-074427
- OAI identifier oai:identifier
- oai:vtechworks.lib.vt.edu:10919/27730