Thermal Characterization of Die-Attach Degradation in the Power MOSFET

The thermal performance of the power MOSFET module is subject to change over its lifetime. This is caused by the growth of voids and other defects in the die-attach layer. The goal of this dissertation is to develop measurement techniques and finite element simulations that can measure the changes in thermal performance caused by changes in die-attach voided area. These experimental results and simulations can then be used to create predictions of the thermal performance of a particular power semiconductor module at various stages of die-attach fatigue. In the results and simulations presented, a relationship is developed between thermal impedance and void area coverage. This dissertation starts by presenting an analysis of the thermal and mechanical stresses needed for crack and void growth in the power semiconductor die-attach region. Accelerated life testing is then performed for both commercial and prototype power semiconductor devices to generate the stresses needed to precipitate void growth. Representative groups of lead and lead-free solders are then tested to compare levels of die-attach degradation under accelerated life conditions. Hardware is developed to experimentally measure thermal impedance using temperaturesensitive characteristics of the power MOSFET. The power semiconductor devices that were subjected to accelerated life testing are then measured with this hardware. The results show that die-attach voided area coverage increases thermal impedance. Representative lumped parameter thermal models that use R-C circuits are derived to demonstrate the ability of the thermal impedance analyzer to determine the differences in the die-attach layer. Finite element modeling (FEM) is then used on representative voided devices to support these results, with additional emphasis on peak temperatures caused by hotspots located over the voided areas. Experimental techniques are further applied to measurement of cooling trends that occur due to the existence of voids in the die-attach layer. These measurements are correlated with finite element thermal simulations to develop a relationship between thermal impedance, hotspot temperature, die-attach void size, and total voided area coverage.

Name thesis:degree_name

Ph. D.

Level thesis:degree_level

doctoral

Discipline thesis:degree_discipline

Electrical and Computer Engineering

Department dc:contributor.department

Electrical and Computer Engineering

Grantor dc:publisher

Virginia Tech

Year dc:date.issued

2003

Author dc:creator

• Katsis, Dimosthenis C.

Chair dc:contributor.committeechair

• van Wyk, Jacobus Daniel

Committee members dc:contributor.committeemember

• Lu, Guo-Quan
• Huang, Alex Q.
• Boroyevich, Dushan
• Lai, Jih-Sheng

• Die-attach Fatigue
• Finite Element Thermal Modeling
• Thermal Impedance

Statement dc:rights

• In Copyright

Licence dc:rights.uri

• http://rightsstatements.org/vocab/InC/1.0/

Dc Identifier Other

etd-02152003-115529

OAI identifier oai:identifier

oai:vtechworks.lib.vt.edu:10919/26206