{"id":{"repo_id":"vt","oai_identifier":"oai:vtechworks.lib.vt.edu:10919/140697"},"canonical_url":"https://search.dev.ndltd.org/etd/vt/oai:vtechworks.lib.vt.edu:10919/140697","repository":{"repo_id":"vt","name":"Virginia Tech","base_url":"https://vtechworks.lib.vt.edu/oai/request"},"display":{"title":"Scalable and Reconfigurable True-Time Delay Line for Integrated Radio-Frequency Recurrent Neural Processors","abstract":"This paper presents a scalable and tunable delay-line architecture for analog recurrent neural networks (RNNs) operating directly in the RF-domain. Previous research has shown the RF-domain RNNs are capable of performing real-time anomaly detection in wireless systems while reducing the inference latency of the wireless system to be one RF clock cycle. The original RF-domain RNN structure relies on a passive tapped transmission line delay for sequential input samples, limiting the architecture's scalability, power efficiency, and frequency adaptability. Transmission lines have too much attenuation, become impractically large for chip integration, and are untunable. To eliminate these limitations, the passive transmission line delay is replaced with an active delay line made up of cascaded gm-C all-pass filter (APF) cells. The APF cells achieve true-time delay while maintaining low attenuation, low power consumption, high linearity, and have reconfigurable delay characteristics. The proposed solution utilizes compact integration, signal preservation along the delay line, and dynamic tuning for different carrier frequencies or true-time delay needs. A full model of the active delay line and it's integration with the RF-RNN architecture is developed in GlobalFoundaries 65-nm BiCMOS technology. The model includes delay characterization, analysis of loading effects, and noise analysis. The simulation results show that the gm-C APF delay network enables scalable RF-RNN implementations while maintaining anomaly classification performance accuracy under realistic timing variations. This work demonstrates a key step towards practical RF-domain neural processors capable of supporting real-time wireless systems for 5G and beyond.","abstract_html":"This paper presents a scalable and tunable delay-line architecture for analog recurrent neural networks (RNNs) operating directly in the RF-domain. Previous research has shown the RF-domain RNNs are capable of performing real-time anomaly detection in wireless systems while reducing the inference latency of the wireless system to be one RF clock cycle. The original RF-domain RNN structure relies on a passive tapped transmission line delay for sequential input samples, limiting the architecture's scalability, power efficiency, and frequency adaptability. Transmission lines have too much attenuation, become impractically large for chip integration, and are untunable. To eliminate these limitations, the passive transmission line delay is replaced with an active delay line made up of cascaded gm-C all-pass filter (APF) cells. The APF cells achieve true-time delay while maintaining low attenuation, low power consumption, high linearity, and have reconfigurable delay characteristics. The proposed solution utilizes compact integration, signal preservation along the delay line, and dynamic tuning for different carrier frequencies or true-time delay needs. A full model of the active delay line and it's integration with the RF-RNN architecture is developed in GlobalFoundaries 65-nm BiCMOS technology. The model includes delay characterization, analysis of loading effects, and noise analysis. The simulation results show that the gm-C APF delay network enables scalable RF-RNN implementations while maintaining anomaly classification performance accuracy under realistic timing variations. This work demonstrates a key step towards practical RF-domain neural processors capable of supporting real-time wireless systems for 5G and beyond.","abstract_has_math":false,"creators":["Merton, Nicholas Andrew"],"institution":"Virginia Tech","degree_name":"Master of Science","degree_level":"masters","degree_discipline":"Electrical Engineering","degree_department":"Electrical Engineering","school":null,"contributors":[],"advisors":[],"committee_chairs":["Ha, Dong S."],"committee_members":["Garcia, Christiana Chamon","Shin, Sook"],"year":2026,"date_issued":"2026-01-08","date_published":"2026-01-08","updated_at":"2026-07-22T22:18:50Z","subjects":["Analog signal processing","artificial intelligence (AI)","Recurrent Neural Networks (RNN)","RF analog processor","RF neural network","Gm-C all-pass filter","Active true-time delay"],"languages":["en"],"rights":["In Copyright"],"rights_urls":["http://rightsstatements.org/vocab/InC/1.0/"],"identifier_entries":[{"key":"dc:identifier.other","label":"Dc Identifier Other","values":["vt_gsexam:45620"],"render_values":[{"text":"vt_gsexam:45620","href":null,"code":true}]}]},"links":{"outbound_url":"https://hdl.handle.net/10919/140697","outbound_label":"Handle","outbound_source":"dc:identifier.uri"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor.committeechair","label":"Committee Chair","values":["Ha, Dong S."]},{"key":"dc:contributor.committeemember","label":"Committee Member","values":["Garcia, Christiana Chamon","Shin, Sook"]},{"key":"dc:contributor.department","label":"Department","values":["Electrical Engineering"]},{"key":"dc:creator","label":"Author","values":["Merton, Nicholas Andrew"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date.accessioned","label":"Dc Date Accessioned","values":["2026-01-09T09:01:57Z"]},{"key":"dc:date.available","label":"Dc Date Available","values":["2026-01-09T09:01:57Z"]},{"key":"dc:date.issued","label":"Date","values":["2026-01-08"]},{"key":"dc:publisher","label":"Institution","values":["Virginia Tech"]},{"key":"dc:type","label":"Dc Type","values":["Thesis"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical Engineering"]},{"key":"thesis:degree_level","label":"Degree Level","values":["masters"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Master of Science"]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["Virginia Polytechnic Institute and State University"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Analog signal processing","artificial intelligence (AI)","Recurrent Neural Networks (RNN)","RF analog processor","RF neural network","Gm-C all-pass filter","Active true-time delay"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language.iso","label":"Language (ISO)","values":["en"]},{"key":"dc:rights","label":"Dc Rights","values":["In Copyright"]},{"key":"dc:rights.uri","label":"Rights URI","values":["http://rightsstatements.org/vocab/InC/1.0/"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier.other","label":"Dc Identifier Other","values":["vt_gsexam:45620"]},{"key":"dc:identifier.uri","label":"Identifier URI","values":["https://hdl.handle.net/10919/140697"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description.abstract","label":"Abstract","values":["This paper presents a scalable and tunable delay-line architecture for analog recurrent neural networks (RNNs) operating directly in the RF-domain. Previous research has shown the RF-domain RNNs are capable of performing real-time anomaly detection in wireless systems while reducing the inference latency of the wireless system to be one RF clock cycle. The original RF-domain RNN structure relies on a passive tapped transmission line delay for sequential input samples, limiting the architecture's scalability, power efficiency, and frequency adaptability. Transmission lines have too much attenuation, become impractically large for chip integration, and are untunable. To eliminate these limitations, the passive transmission line delay is replaced with an active delay line made up of cascaded gm-C all-pass filter (APF) cells. The APF cells achieve true-time delay while maintaining low attenuation, low power consumption, high linearity, and have reconfigurable delay characteristics. The proposed solution utilizes compact integration, signal preservation along the delay line, and dynamic tuning for different carrier frequencies or true-time delay needs. A full model of the active delay line and it's integration with the RF-RNN architecture is developed in GlobalFoundaries 65-nm BiCMOS technology. The model includes delay characterization, analysis of loading effects, and noise analysis. The simulation results show that the gm-C APF delay network enables scalable RF-RNN implementations while maintaining anomaly classification performance accuracy under realistic timing variations. This work demonstrates a key step towards practical RF-domain neural processors capable of supporting real-time wireless systems for 5G and beyond."]},{"key":"dc:description.abstractgeneral","label":"General Abstract","values":["This paper presents an analog circuit implementation of a compact and tunable delay line for recurrent neural networks (RNNs) designed entirely in the radio-frequency (RF) domain. Previous research proves that a fully RF implementation of an RNN (referred to as RF-RNN) is able to identify and classify irregularities in incoming RF signals while greatly reducing the processing time. The previous RF-RNN implementation used a transmission line to delay the input RF signal for real-time sampling of the signal. The transmission line however, imposed many constraints on RF-RNN system including the inability to scale larger due the area inefficiency of the transmission line, the reduction of the input signal's amplitude, and inability to adapt to different input frequencies. To solve these constraints, the transmission line is replaced with the proposed active gm-C all-pass filter (APF) delay circuit. The APF circuit has a compact design, little effect on the input signal's amplitude, and can be adjusted for a range of input frequencies or desired delays. A full model of the active APF delay circuit is developed and it's delay, implementation to the RF-RNN, and non-ideal side effects, such as the introduction of unwanted delay variation, is tested and analyzed. The results show improvements in the RF-RNNs scalability and adaptability while maintaining accuracy for identifying and classifying irregularities. This work demonstrates a key step towards implementing RF-domain RNNs into the wireless communication systems of today and the future."]},{"key":"dc:description.degree","label":"Dc Description Degree","values":["Master of Science"]},{"key":"dc:format.medium","label":"Dc Format Medium","values":["ETD"]},{"key":"dc:title","label":"Title","values":["Scalable and Reconfigurable True-Time Delay Line for Integrated Radio-Frequency Recurrent Neural Processors"]}]}],"canonical_facts":{"dc:contributor.committeechair":["Ha, Dong S."],"dc:contributor.committeemember":["Garcia, Christiana Chamon","Shin, Sook"],"dc:contributor.department":["Electrical Engineering"],"dc:creator":["Merton, Nicholas Andrew"],"dc:date.accessioned":["2026-01-09T09:01:57Z"],"dc:date.available":["2026-01-09T09:01:57Z"],"dc:date.issued":["2026-01-08"],"dc:description.abstract":["This paper presents a scalable and tunable delay-line architecture for analog recurrent neural networks (RNNs) operating directly in the RF-domain. Previous research has shown the RF-domain RNNs are capable of performing real-time anomaly detection in wireless systems while reducing the inference latency of the wireless system to be one RF clock cycle. The original RF-domain RNN structure relies on a passive tapped transmission line delay for sequential input samples, limiting the architecture's scalability, power efficiency, and frequency adaptability. Transmission lines have too much attenuation, become impractically large for chip integration, and are untunable. To eliminate these limitations, the passive transmission line delay is replaced with an active delay line made up of cascaded gm-C all-pass filter (APF) cells. The APF cells achieve true-time delay while maintaining low attenuation, low power consumption, high linearity, and have reconfigurable delay characteristics. The proposed solution utilizes compact integration, signal preservation along the delay line, and dynamic tuning for different carrier frequencies or true-time delay needs. A full model of the active delay line and it's integration with the RF-RNN architecture is developed in GlobalFoundaries 65-nm BiCMOS technology. The model includes delay characterization, analysis of loading effects, and noise analysis. The simulation results show that the gm-C APF delay network enables scalable RF-RNN implementations while maintaining anomaly classification performance accuracy under realistic timing variations. This work demonstrates a key step towards practical RF-domain neural processors capable of supporting real-time wireless systems for 5G and beyond."],"dc:description.abstractgeneral":["This paper presents an analog circuit implementation of a compact and tunable delay line for recurrent neural networks (RNNs) designed entirely in the radio-frequency (RF) domain. Previous research proves that a fully RF implementation of an RNN (referred to as RF-RNN) is able to identify and classify irregularities in incoming RF signals while greatly reducing the processing time. The previous RF-RNN implementation used a transmission line to delay the input RF signal for real-time sampling of the signal. The transmission line however, imposed many constraints on RF-RNN system including the inability to scale larger due the area inefficiency of the transmission line, the reduction of the input signal's amplitude, and inability to adapt to different input frequencies. To solve these constraints, the transmission line is replaced with the proposed active gm-C all-pass filter (APF) delay circuit. The APF circuit has a compact design, little effect on the input signal's amplitude, and can be adjusted for a range of input frequencies or desired delays. A full model of the active APF delay circuit is developed and it's delay, implementation to the RF-RNN, and non-ideal side effects, such as the introduction of unwanted delay variation, is tested and analyzed. The results show improvements in the RF-RNNs scalability and adaptability while maintaining accuracy for identifying and classifying irregularities. This work demonstrates a key step towards implementing RF-domain RNNs into the wireless communication systems of today and the future."],"dc:description.degree":["Master of Science"],"dc:format.medium":["ETD"],"dc:identifier.other":["vt_gsexam:45620"],"dc:identifier.uri":["https://hdl.handle.net/10919/140697"],"dc:language.iso":["en"],"dc:publisher":["Virginia Tech"],"dc:rights":["In Copyright"],"dc:rights.uri":["http://rightsstatements.org/vocab/InC/1.0/"],"dc:subject":["Analog signal processing","artificial intelligence (AI)","Recurrent Neural Networks (RNN)","RF analog processor","RF neural network","Gm-C all-pass filter","Active true-time delay"],"dc:title":["Scalable and Reconfigurable True-Time Delay Line for Integrated Radio-Frequency Recurrent Neural Processors"],"dc:type":["Thesis"],"thesis:degree_discipline":["Electrical Engineering"],"thesis:degree_level":["masters"],"thesis:degree_name":["Master of Science"],"thesis:institution_name":["Virginia Polytechnic Institute and State University"]},"updated_at":"2026-07-22T22:18:50Z"}