{"id":{"repo_id":"vt","oai_identifier":"oai:vtechworks.lib.vt.edu:10919/139937"},"canonical_url":"https://search.dev.ndltd.org/etd/vt/oai:vtechworks.lib.vt.edu:10919/139937","repository":{"repo_id":"vt","name":"Virginia Tech","base_url":"https://vtechworks.lib.vt.edu/oai/request"},"display":{"title":"Enabling Energy-Efficient Hybrid CMOS and Embedded Memory Accelerators for Neuromorphic Computing at the Edge","abstract":"The deployment of deep learning at the edge promises advances in autonomous driving, computer vision, and IoT, but is limited by the inefficiencies of conventional von Neumann architectures. The physical separation of memory and processing creates a performance bottleneck, with high energy and latency costs. This dissertation investigates hybrid CMOS–memristor accelerators that leverage non von Neumann paradigms to address these constraints. The first contribution explores computing-in-memory (CIM) architectures using memristors, which combine storage and computation to reduce data movement. While memristors offer density, low power, and nonvolatility, challenges such as resistance variation degrade inference accuracy. To mitigate this, novel two-layer memristor structures with improved thermal properties are proposed to enhance reliability. The second focus is on integrating spiking neural networks (SNNs) with memristor crossbars. By mimicking biological spike-based communication, SNNs improve robustness and energy efficiency. New encoding schemes and Leaky Integrate-and-Fire (LIF) neuron models are developed to optimize temporal information processing. We then explore reservoir computing (RC) architecture to reduce the training complexity of deep models on ASICs. By training only the output layer while preserving spatiotemporal dynamics in the reservoir, RC reduces hardware cost and time while maintaining performance. The proposed architectures are evaluated on edge applications, including autonomous driving and image recognition, where energy efficiency, adaptability, and reliability are critical. Results show that these reconfigurable accelerators improve accuracy and robustness while meeting strict power and area constraints, advancing the design of scalable edge AI hardware.","abstract_html":"The deployment of deep learning at the edge promises advances in autonomous driving, computer vision, and IoT, but is limited by the inefficiencies of conventional von Neumann architectures. The physical separation of memory and processing creates a performance bottleneck, with high energy and latency costs. This dissertation investigates hybrid CMOS–memristor accelerators that leverage non von Neumann paradigms to address these constraints. The first contribution explores computing-in-memory (CIM) architectures using memristors, which combine storage and computation to reduce data movement. While memristors offer density, low power, and nonvolatility, challenges such as resistance variation degrade inference accuracy. To mitigate this, novel two-layer memristor structures with improved thermal properties are proposed to enhance reliability. The second focus is on integrating spiking neural networks (SNNs) with memristor crossbars. By mimicking biological spike-based communication, SNNs improve robustness and energy efficiency. New encoding schemes and Leaky Integrate-and-Fire (LIF) neuron models are developed to optimize temporal information processing. We then explore reservoir computing (RC) architecture to reduce the training complexity of deep models on ASICs. By training only the output layer while preserving spatiotemporal dynamics in the reservoir, RC reduces hardware cost and time while maintaining performance. The proposed architectures are evaluated on edge applications, including autonomous driving and image recognition, where energy efficiency, adaptability, and reliability are critical. Results show that these reconfigurable accelerators improve accuracy and robustness while meeting strict power and area constraints, advancing the design of scalable edge AI hardware.","abstract_has_math":false,"creators":["Nowshin, Fabiha"],"institution":"Virginia Tech","degree_name":"Doctor of Philosophy","degree_level":"doctoral","degree_discipline":"Electrical Engineering","degree_department":"Electrical Engineering","school":null,"contributors":[],"advisors":[],"committee_chairs":["Yi, Yang"],"committee_members":["Davalos, Rafael V.","Liu, Lingjia","Ha, Dong S.","Jia, Xiaoting"],"year":2025,"date_issued":"2025-12-16","date_published":"2025-12-16","updated_at":"2026-07-24T05:56:34Z","subjects":["neuromorphic computing","analog integrated circuit design","edge devices","reservoir computing","spiking neural networks","computing-in-memory","emerging memory"],"languages":["en"],"rights":["In Copyright"],"rights_urls":["http://rightsstatements.org/vocab/InC/1.0/"],"identifier_entries":[{"key":"dc:identifier.other","label":"Dc Identifier Other","values":["vt_gsexam:44695"],"render_values":[{"text":"vt_gsexam:44695","href":null,"code":true}]}]},"links":{"outbound_url":"https://hdl.handle.net/10919/139937","outbound_label":"Handle","outbound_source":"dc:identifier.uri"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor.committeechair","label":"Committee Chair","values":["Yi, Yang"]},{"key":"dc:contributor.committeemember","label":"Committee Member","values":["Davalos, Rafael V.","Liu, Lingjia","Ha, Dong S.","Jia, Xiaoting"]},{"key":"dc:contributor.department","label":"Department","values":["Electrical Engineering"]},{"key":"dc:creator","label":"Author","values":["Nowshin, Fabiha"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date.accessioned","label":"Dc Date Accessioned","values":["2025-12-17T09:00:55Z"]},{"key":"dc:date.available","label":"Dc Date Available","values":["2025-12-17T09:00:55Z"]},{"key":"dc:date.issued","label":"Date","values":["2025-12-16"]},{"key":"dc:publisher","label":"Institution","values":["Virginia Tech"]},{"key":"dc:type","label":"Dc Type","values":["Dissertation"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical Engineering"]},{"key":"thesis:degree_level","label":"Degree Level","values":["doctoral"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Doctor of Philosophy"]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["Virginia Polytechnic Institute and State University"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["neuromorphic computing","analog integrated circuit design","edge devices","reservoir computing","spiking neural networks","computing-in-memory","emerging memory"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language.iso","label":"Language (ISO)","values":["en"]},{"key":"dc:rights","label":"Dc Rights","values":["In Copyright"]},{"key":"dc:rights.uri","label":"Rights URI","values":["http://rightsstatements.org/vocab/InC/1.0/"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier.other","label":"Dc Identifier Other","values":["vt_gsexam:44695"]},{"key":"dc:identifier.uri","label":"Identifier URI","values":["https://hdl.handle.net/10919/139937"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description.abstract","label":"Abstract","values":["The deployment of deep learning at the edge promises advances in autonomous driving, computer vision, and IoT, but is limited by the inefficiencies of conventional von Neumann architectures. The physical separation of memory and processing creates a performance bottleneck, with high energy and latency costs. This dissertation investigates hybrid CMOS–memristor accelerators that leverage non von Neumann paradigms to address these constraints. The first contribution explores computing-in-memory (CIM) architectures using memristors, which combine storage and computation to reduce data movement. While memristors offer density, low power, and nonvolatility, challenges such as resistance variation degrade inference accuracy. To mitigate this, novel two-layer memristor structures with improved thermal properties are proposed to enhance reliability. The second focus is on integrating spiking neural networks (SNNs) with memristor crossbars. By mimicking biological spike-based communication, SNNs improve robustness and energy efficiency. New encoding schemes and Leaky Integrate-and-Fire (LIF) neuron models are developed to optimize temporal information processing. We then explore reservoir computing (RC) architecture to reduce the training complexity of deep models on ASICs. By training only the output layer while preserving spatiotemporal dynamics in the reservoir, RC reduces hardware cost and time while maintaining performance. The proposed architectures are evaluated on edge applications, including autonomous driving and image recognition, where energy efficiency, adaptability, and reliability are critical. Results show that these reconfigurable accelerators improve accuracy and robustness while meeting strict power and area constraints, advancing the design of scalable edge AI hardware."]},{"key":"dc:description.abstractgeneral","label":"General Abstract","values":["The integration of artificial intelligence (AI) into devices ranging from smartphones to self-driving cars has opened new frontiers in technology. Yet, bringing AI to small, portable, or real-time systems, known as edge devices, remains a challenge. Unlike data centers, edge devices must process information rapidly with limited energy. Traditional von Neumann architectures, which separate memory and processing, struggle with the heavy data movement required by AI, resulting in wasted time and power. This dissertation explores neuromorphic chip designs that are efficient, compact, and tailored for edge applications. A central focus is computing-in-memory (CIM), where data is processed directly in or near memory, reducing costly transfers. The research also investigates spiking neural networks (SNNs), which mimic how the brain encodes information with spikes. Integrating SNNs with embedded memory-based circuits enables higher robustness and energy efficiency. To simplify training, a reservoir computing architecture is also explored, which trains only the output layer, cutting hardware cost and complexity. Finally, the dissertation demonstrates these approaches in real-world edge applications, including autonomous driving and image recognition, where real-time decision-making is critical. The goal is to design reconfigurable, energy-efficient accelerators that improve accuracy, reliability, and safety, bringing advanced AI capabilities to resource-constrained devices."]},{"key":"dc:description.degree","label":"Dc Description Degree","values":["Doctor of Philosophy"]},{"key":"dc:format.medium","label":"Dc Format Medium","values":["ETD"]},{"key":"dc:title","label":"Title","values":["Enabling Energy-Efficient Hybrid CMOS and Embedded Memory Accelerators for Neuromorphic Computing at the Edge"]}]}],"canonical_facts":{"dc:contributor.committeechair":["Yi, Yang"],"dc:contributor.committeemember":["Davalos, Rafael V.","Liu, Lingjia","Ha, Dong S.","Jia, Xiaoting"],"dc:contributor.department":["Electrical Engineering"],"dc:creator":["Nowshin, Fabiha"],"dc:date.accessioned":["2025-12-17T09:00:55Z"],"dc:date.available":["2025-12-17T09:00:55Z"],"dc:date.issued":["2025-12-16"],"dc:description.abstract":["The deployment of deep learning at the edge promises advances in autonomous driving, computer vision, and IoT, but is limited by the inefficiencies of conventional von Neumann architectures. The physical separation of memory and processing creates a performance bottleneck, with high energy and latency costs. This dissertation investigates hybrid CMOS–memristor accelerators that leverage non von Neumann paradigms to address these constraints. The first contribution explores computing-in-memory (CIM) architectures using memristors, which combine storage and computation to reduce data movement. While memristors offer density, low power, and nonvolatility, challenges such as resistance variation degrade inference accuracy. To mitigate this, novel two-layer memristor structures with improved thermal properties are proposed to enhance reliability. The second focus is on integrating spiking neural networks (SNNs) with memristor crossbars. By mimicking biological spike-based communication, SNNs improve robustness and energy efficiency. New encoding schemes and Leaky Integrate-and-Fire (LIF) neuron models are developed to optimize temporal information processing. We then explore reservoir computing (RC) architecture to reduce the training complexity of deep models on ASICs. By training only the output layer while preserving spatiotemporal dynamics in the reservoir, RC reduces hardware cost and time while maintaining performance. The proposed architectures are evaluated on edge applications, including autonomous driving and image recognition, where energy efficiency, adaptability, and reliability are critical. Results show that these reconfigurable accelerators improve accuracy and robustness while meeting strict power and area constraints, advancing the design of scalable edge AI hardware."],"dc:description.abstractgeneral":["The integration of artificial intelligence (AI) into devices ranging from smartphones to self-driving cars has opened new frontiers in technology. Yet, bringing AI to small, portable, or real-time systems, known as edge devices, remains a challenge. Unlike data centers, edge devices must process information rapidly with limited energy. Traditional von Neumann architectures, which separate memory and processing, struggle with the heavy data movement required by AI, resulting in wasted time and power. This dissertation explores neuromorphic chip designs that are efficient, compact, and tailored for edge applications. A central focus is computing-in-memory (CIM), where data is processed directly in or near memory, reducing costly transfers. The research also investigates spiking neural networks (SNNs), which mimic how the brain encodes information with spikes. Integrating SNNs with embedded memory-based circuits enables higher robustness and energy efficiency. To simplify training, a reservoir computing architecture is also explored, which trains only the output layer, cutting hardware cost and complexity. Finally, the dissertation demonstrates these approaches in real-world edge applications, including autonomous driving and image recognition, where real-time decision-making is critical. The goal is to design reconfigurable, energy-efficient accelerators that improve accuracy, reliability, and safety, bringing advanced AI capabilities to resource-constrained devices."],"dc:description.degree":["Doctor of Philosophy"],"dc:format.medium":["ETD"],"dc:identifier.other":["vt_gsexam:44695"],"dc:identifier.uri":["https://hdl.handle.net/10919/139937"],"dc:language.iso":["en"],"dc:publisher":["Virginia Tech"],"dc:rights":["In Copyright"],"dc:rights.uri":["http://rightsstatements.org/vocab/InC/1.0/"],"dc:subject":["neuromorphic computing","analog integrated circuit design","edge devices","reservoir computing","spiking neural networks","computing-in-memory","emerging memory"],"dc:title":["Enabling Energy-Efficient Hybrid CMOS and Embedded Memory Accelerators for Neuromorphic Computing at the Edge"],"dc:type":["Dissertation"],"thesis:degree_discipline":["Electrical Engineering"],"thesis:degree_level":["doctoral"],"thesis:degree_name":["Doctor of Philosophy"],"thesis:institution_name":["Virginia Polytechnic Institute and State University"]},"updated_at":"2026-07-24T05:56:34Z"}