{"id":{"repo_id":"vt","oai_identifier":"oai:vtechworks.lib.vt.edu:10919/111039"},"canonical_url":"https://search.dev.ndltd.org/etd/vt/oai:vtechworks.lib.vt.edu:10919/111039","repository":{"repo_id":"vt","name":"Virginia Tech","base_url":"https://vtechworks.lib.vt.edu/oai/request"},"display":{"title":"Selection of flip-flops for partial scan design","abstract":"Partial scan has served as an alternative solution for test generation for sequential circuits. As only a portion of flip-flops are incorporated into a scan chain in partial scan design, scan flip-flop selection constitutes a key procedure in partial scan. In this thesis, we propose a new way of selecting scan flip-flops, the Extended Tracking Algorithm (ETA). ETA is a test generation based method and aims to find the conditions that can lead to the detection of as many aborted faults as possible. The faults aborted by a sequential automatic test pattern generator (ATPG) are targeted in ETA and the requirements for the detection of the faults are used for the selection of scan flip-flops. The Extended Tracking Algorithm is realized in two different algorithms, optimal and heuristic, depending on the objectives. The optimal algorithm guarantees the minimal set of flip-flops for the detection of all of the aborted faults in a given circuit, but it has exponential worst case complexity. The heuristic algorithm, on the other hand, obtains a near optimal solution in shorter time. ETA provides a spectrum of accurate fault efficiency and/or fault coverage so that the designer can choose an affordable option. The method is simple and compatible with other scan flip-flop selection approaches. We implemented the Extended Tracking Algorithm in a program called BELLONA. Experiments have been conducted on ISCAS89 benchmark circuits with different specifications. Our experimental results show that ETA is an efficient solution for partial scan deign and only a small portion of scan flip-flops are necessary to obtain extremely high fault efficiency.","abstract_html":"Partial scan has served as an alternative solution for test generation for sequential circuits. As only a portion of flip-flops are incorporated into a scan chain in partial scan design, scan flip-flop selection constitutes a key procedure in partial scan. In this thesis, we propose a new way of selecting scan flip-flops, the Extended Tracking Algorithm (ETA). ETA is a test generation based method and aims to find the conditions that can lead to the detection of as many aborted faults as possible. The faults aborted by a sequential automatic test pattern generator (ATPG) are targeted in ETA and the requirements for the detection of the faults are used for the selection of scan flip-flops. The Extended Tracking Algorithm is realized in two different algorithms, optimal and heuristic, depending on the objectives. The optimal algorithm guarantees the minimal set of flip-flops for the detection of all of the aborted faults in a given circuit, but it has exponential worst case complexity. The heuristic algorithm, on the other hand, obtains a near optimal solution in shorter time. ETA provides a spectrum of accurate fault efficiency and/or fault coverage so that the designer can choose an affordable option. The method is simple and compatible with other scan flip-flop selection approaches. We implemented the Extended Tracking Algorithm in a program called BELLONA. Experiments have been conducted on ISCAS89 benchmark circuits with different specifications. Our experimental results show that ETA is an efficient solution for partial scan deign and only a small portion of scan flip-flops are necessary to obtain extremely high fault efficiency.","abstract_has_math":false,"creators":["Park, Insung"],"institution":"Virginia Polytechnic Institute and State University","degree_name":"M.S.","degree_level":"masters","degree_discipline":"Electrical Engineering","degree_department":"Electrical Engineering","school":null,"contributors":[],"advisors":[],"committee_chairs":[],"committee_members":[],"year":1994,"date_issued":"1994","date_published":"1994","updated_at":"2026-07-22T22:19:54Z","subjects":[],"languages":["en"],"rights":["In Copyright"],"rights_urls":["http://rightsstatements.org/vocab/InC/1.0/"],"identifier_entries":[]},"links":{"outbound_url":"http://hdl.handle.net/10919/111039","outbound_label":"Handle","outbound_source":"dc:identifier.uri"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor.department","label":"Department","values":["Electrical Engineering"]},{"key":"dc:creator","label":"Author","values":["Park, Insung"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date.accessioned","label":"Dc Date Accessioned","values":["2022-06-29T19:26:48Z"]},{"key":"dc:date.available","label":"Dc Date Available","values":["2022-06-29T19:26:48Z"]},{"key":"dc:date.issued","label":"Date","values":["1994"]},{"key":"dc:publisher","label":"Institution","values":["Virginia Polytechnic Institute and State University"]},{"key":"dc:type","label":"Dc Type","values":["Thesis"]},{"key":"dc:type.dcmitype","label":"Dc Type Dcmitype","values":["Text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical Engineering"]},{"key":"thesis:degree_level","label":"Degree Level","values":["masters"]},{"key":"thesis:degree_name","label":"Degree Name","values":["M.S."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["Virginia Polytechnic Institute and State University"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language.iso","label":"Language (ISO)","values":["en"]},{"key":"dc:rights","label":"Dc Rights","values":["In Copyright"]},{"key":"dc:rights.uri","label":"Rights URI","values":["http://rightsstatements.org/vocab/InC/1.0/"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier.uri","label":"Identifier URI","values":["http://hdl.handle.net/10919/111039"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description.abstract","label":"Abstract","values":["Partial scan has served as an alternative solution for test generation for sequential circuits. As only a portion of flip-flops are incorporated into a scan chain in partial scan design, scan flip-flop selection constitutes a key procedure in partial scan. In this thesis, we propose a new way of selecting scan flip-flops, the Extended Tracking Algorithm (ETA). ETA is a test generation based method and aims to find the conditions that can lead to the detection of as many aborted faults as possible. The faults aborted by a sequential automatic test pattern generator (ATPG) are targeted in ETA and the requirements for the detection of the faults are used for the selection of scan flip-flops. The Extended Tracking Algorithm is realized in two different algorithms, optimal and heuristic, depending on the objectives. The optimal algorithm guarantees the minimal set of flip-flops for the detection of all of the aborted faults in a given circuit, but it has exponential worst case complexity. The heuristic algorithm, on the other hand, obtains a near optimal solution in shorter time. ETA provides a spectrum of accurate fault efficiency and/or fault coverage so that the designer can choose an affordable option. The method is simple and compatible with other scan flip-flop selection approaches. We implemented the Extended Tracking Algorithm in a program called BELLONA. Experiments have been conducted on ISCAS89 benchmark circuits with different specifications. Our experimental results show that ETA is an efficient solution for partial scan deign and only a small portion of scan flip-flops are necessary to obtain extremely high fault efficiency."]},{"key":"dc:description.degree","label":"Dc Description Degree","values":["M.S."]},{"key":"dc:format.mimetype","label":"Dc Format Mimetype","values":["application/pdf"]},{"key":"dc:title","label":"Title","values":["Selection of flip-flops for partial scan design"]}]}],"canonical_facts":{"dc:contributor.department":["Electrical Engineering"],"dc:creator":["Park, Insung"],"dc:date.accessioned":["2022-06-29T19:26:48Z"],"dc:date.available":["2022-06-29T19:26:48Z"],"dc:date.issued":["1994"],"dc:description.abstract":["Partial scan has served as an alternative solution for test generation for sequential circuits. As only a portion of flip-flops are incorporated into a scan chain in partial scan design, scan flip-flop selection constitutes a key procedure in partial scan. In this thesis, we propose a new way of selecting scan flip-flops, the Extended Tracking Algorithm (ETA). ETA is a test generation based method and aims to find the conditions that can lead to the detection of as many aborted faults as possible. The faults aborted by a sequential automatic test pattern generator (ATPG) are targeted in ETA and the requirements for the detection of the faults are used for the selection of scan flip-flops. The Extended Tracking Algorithm is realized in two different algorithms, optimal and heuristic, depending on the objectives. The optimal algorithm guarantees the minimal set of flip-flops for the detection of all of the aborted faults in a given circuit, but it has exponential worst case complexity. The heuristic algorithm, on the other hand, obtains a near optimal solution in shorter time. ETA provides a spectrum of accurate fault efficiency and/or fault coverage so that the designer can choose an affordable option. The method is simple and compatible with other scan flip-flop selection approaches. We implemented the Extended Tracking Algorithm in a program called BELLONA. Experiments have been conducted on ISCAS89 benchmark circuits with different specifications. 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