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Virginia Polytechnic Institute and State University

Multimodule simulation techniques for chip level modeling

Abstract

dc:description.abstract

A design and implementation of a multimodule chip-level simulator whose source description language is based on the original GSP2 system is described. To enhance the simulation speed, a special addressing ("sharing single memory location") scheme is used in the implementation of pin connections. The basic data structures and algorithms for the simulator are described. The developed simulator can simulate many digital devices interconnected as a digital network. It also has the capability of modeling external buses and handling the suspension of processes in the environment of multimodule simulation. An example of a multimodule digital system simulation is presented.

Degree

thesis:*
Name thesis:degree_name
M.S.
Level thesis:degree_level
masters
Discipline thesis:degree_discipline
Electrical Engineering
Department dc:contributor.department
Electrical Engineering
Grantor dc:publisher
Virginia Polytechnic Institute and State University
Year dc:date.issued
1986

Author and committee

dc:creator, dc:contributor.*
Author dc:creator
  • Cho, Chang H.

Rights

dc:rights
Statement dc:rights
  • In Copyright
Language dc:language.iso
en

Identifiers

dc:identifier.*
Handle dc:identifier.uri
http://hdl.handle.net/10919/106085
OAI identifier oai:identifier
oai:vtechworks.lib.vt.edu:10919/106085

Chain of custody

source
Harvested from
Virginia Tech
Base URL
vtechworks.lib.vt.edu/oai/request
Last updated
2026-07-22
Source record
OAI-PMH GetRecord
related terms
citation

Cho, Chang H.. Multimodule simulation techniques for chip level modeling. masters thesis, Virginia Polytechnic Institute and State University, 1986. http://hdl.handle.net/10919/106085