{"id":{"repo_id":"vt","oai_identifier":"oai:vtechworks.lib.vt.edu:10919/105995"},"canonical_url":"https://search.dev.ndltd.org/etd/vt/oai:vtechworks.lib.vt.edu:10919/105995","repository":{"repo_id":"vt","name":"Virginia Tech","base_url":"https://vtechworks.lib.vt.edu/oai/request"},"display":{"title":"Automated collection of vehicular delay data at intersections","abstract":"Most current methods used for the estimation of vehicular delay at intersections involve some form of manual data collection. These methods rely on statistical correlation to improve the accuracy of the delay estimates. In addition, most require significant data collection and reduction efforts. This work presents the theory, design, and operation of a microprocessor-based system for the collection of vehicular delay data at intersections. The hardware design is described in detail including schematic diagrams of the microprocessor system and the associated interface circuitry. Documented software listings and flowcharts are provided as well as a description of the data collection and reduction processes. A benefit/cost analysis was made based on the construction and operation of a prototype system. The system performance was evaluated both in the lab and through analysis of data collected in the field. Recommendations for further development of the device are presented as well as applications of the microprocessor to other forms of transportation and traffic engineering data.","abstract_html":"Most current methods used for the estimation of vehicular delay at intersections involve some form of manual data collection. These methods rely on statistical correlation to improve the accuracy of the delay estimates. In addition, most require significant data collection and reduction efforts. This work presents the theory, design, and operation of a microprocessor-based system for the collection of vehicular delay data at intersections. The hardware design is described in detail including schematic diagrams of the microprocessor system and the associated interface circuitry. Documented software listings and flowcharts are provided as well as a description of the data collection and reduction processes. A benefit/cost analysis was made based on the construction and operation of a prototype system. The system performance was evaluated both in the lab and through analysis of data collected in the field. Recommendations for further development of the device are presented as well as applications of the microprocessor to other forms of transportation and traffic engineering data.","abstract_has_math":false,"creators":["Legere, Jay Francis"],"institution":"Virginia Polytechnic Institute and State University","degree_name":"M.S.","degree_level":"masters","degree_discipline":"Civil Engineering","degree_department":"Civil Engineering","school":null,"contributors":[],"advisors":[],"committee_chairs":[],"committee_members":[],"year":1983,"date_issued":"1983","date_published":"1983","updated_at":"2026-07-22T22:20:09Z","subjects":[],"languages":["en"],"rights":["In Copyright"],"rights_urls":["http://rightsstatements.org/vocab/InC/1.0/"],"identifier_entries":[]},"links":{"outbound_url":"http://hdl.handle.net/10919/105995","outbound_label":"Handle","outbound_source":"dc:identifier.uri"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor.department","label":"Department","values":["Civil Engineering"]},{"key":"dc:creator","label":"Author","values":["Legere, Jay Francis"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date.accessioned","label":"Dc Date Accessioned","values":["2021-10-26T20:09:46Z"]},{"key":"dc:date.available","label":"Dc Date Available","values":["2021-10-26T20:09:46Z"]},{"key":"dc:date.issued","label":"Date","values":["1983"]},{"key":"dc:publisher","label":"Institution","values":["Virginia Polytechnic Institute and State University"]},{"key":"dc:type","label":"Dc Type","values":["Thesis"]},{"key":"dc:type.dcmitype","label":"Dc Type Dcmitype","values":["Text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Civil Engineering"]},{"key":"thesis:degree_level","label":"Degree Level","values":["masters"]},{"key":"thesis:degree_name","label":"Degree Name","values":["M.S."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["Virginia Polytechnic Institute and State University"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language.iso","label":"Language (ISO)","values":["en"]},{"key":"dc:rights","label":"Dc Rights","values":["In Copyright"]},{"key":"dc:rights.uri","label":"Rights URI","values":["http://rightsstatements.org/vocab/InC/1.0/"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier.uri","label":"Identifier URI","values":["http://hdl.handle.net/10919/105995"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description.abstract","label":"Abstract","values":["Most current methods used for the estimation of vehicular delay at intersections involve some form of manual data collection. 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In addition, most require significant data collection and reduction efforts. This work presents the theory, design, and operation of a microprocessor-based system for the collection of vehicular delay data at intersections. The hardware design is described in detail including schematic diagrams of the microprocessor system and the associated interface circuitry. Documented software listings and flowcharts are provided as well as a description of the data collection and reduction processes. A benefit/cost analysis was made based on the construction and operation of a prototype system. The system performance was evaluated both in the lab and through analysis of data collected in the field. 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