Performance Analysis of Multicomputer Interconnection Network Designs

In this thesis, the design and performance issues of multicomputer interconnection networks are addressed. Analytic models are used to evaluate the performance of large scale multicomputer networks. Performance is measured as the average end-to-end delay between communicating nodes. The models consider the communication processing queueing delays experienced by packets at each node as well as delays associated with transmission of packets. A comparison study of message switching and cut-through switching is presented. It is shown, conforming to previous studies, that a network has superior performance when cut-through switching is used. Cut-through switching is most advantageous when the network load is low and degenerates to message switching performance under heavy network loads. The network model is used to develop a "Network Analyzer", an interactive program that allows analysis of different network designs and workloads. Torus and spanning bus hypercube networks are then analyzed by the program to study the effect of various network parameters, traffic patterns, and switching techniques on network delay performance. The Network Analyzer is relatively easy to learn and use, and once learned, it is easy to change network parameters to perform a trade-off study of design alternatives. The program can also be used to quickly generate listings and graphics to illustrate the results of the analysis. The program proved to be an efficient design tool. Hypercube topologies are the most popular for large scale parallel computers, particularly for computationally intensive applications. The torus and spanning bus hypercubes are implemented in our program and analyzed in detail. Results show that network topology has a mixed impact on system performance. Networks built of standard modules of spanning bus hypercubes are harder to expand, compared to a torus network, but they have lower connection cost per node. Communication delays are generally higher for spanning bus networks except at very low traffic loads.

Name thesis:degree_name

M.S.

Level thesis:degree_level

masters

Discipline thesis:degree_discipline

Electrical Engineering

Department dc:contributor.department

Electrical Engineering

Grantor dc:publisher

Virginia Polytechnic Institute and State University

Year dc:date.issued

1987

Author dc:creator

• Abdalla, Hassan Z.

Statement dc:rights

• In Copyright

Licence dc:rights.uri

• http://rightsstatements.org/vocab/InC/1.0/

Language dc:language.iso

en

Handle dc:identifier.uri

http://hdl.handle.net/10919/101364

OAI identifier oai:identifier

oai:vtechworks.lib.vt.edu:10919/101364