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The University of Western Ontario

High Speed and Low-Complexity Hardware Architectures for Elliptic Curve-Based Crypto-Processors

Abstract

dc:description.abstract

The elliptic curve cryptography (ECC) has been identified as an efficient scheme for public-key cryptography. This thesis studies efficient implementation of ECC crypto-processors on hardware platforms in a bottom-up approach. We first study efficient and low-complexity architectures for finite field multiplications over Gaussian normal basis (GNB). We propose three new low-complexity digit-level architectures for finite field multiplication. Architectures are modified in order to make them more suitable for hardware implementations specially focusing on reducing the area usage. Then, for the first time, we propose a hybrid digit-level multiplier architecture which performs two multiplications together (double-multiplication) with the same number of clock cycles required as the one for one multiplication. We propose a new hardware architecture for point multiplication on newly introduced binary Edwards and generalized Hessian curves. We investigate higher level parallelization and lower level scheduling for point multiplication on these curves. Also, we propose a highly parallel architecture for point multiplication on Koblitz curves by modifying the addition formulation. Several FPGA implementations exploiting these modifications are presented in this thesis. We employed the proposed hybrid multiplier architecture to reduce the latency of point multiplication in ECC crypto-processors as well as the double-exponentiation. This scheme is the first known method to increase the speed of point multiplication whenever parallelization fails due to the data dependencies amongst lower level arithmetic computations. Our comparison results show that our proposed multiplier architectures outperform the counterparts available in the literature. Furthermore, fast computation of point multiplication on different binary elliptic curves is achieved.

Degree

thesis:*
Name thesis:degree_name
Ph D
Discipline thesis:degree_discipline
Electrical and Computer Engineering
Grantor dc:publisher
The University of Western Ontario
Year dc:date.issued
2011

Author and committee

dc:creator, dc:contributor.*
Author dc:creator
  • Azarderakhsh, Reza
Advisor dc:contributor.advisor
  • Reyhani-Masoleh, Arash

Subjects

dc:subject × 5

Rights

Language dc:language.iso
en_ca

Identifiers

dc:identifier.*
OAI identifier oai:identifier
oai:uwo.scholaris.ca:20.500.14721/36053

Chain of custody

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Harvested from
Western University
Base URL
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Last updated
2026-07-27
Source record
OAI-PMH GetRecord
citation

Azarderakhsh, Reza. High Speed and Low-Complexity Hardware Architectures for Elliptic Curve-Based Crypto-Processors. The University of Western Ontario, 2011. https://hdl.handle.net/20.500.14721/36053