{"id":{"repo_id":"uwo","oai_identifier":"oai:uwo.scholaris.ca:20.500.14721/35877"},"canonical_url":"https://search.dev.ndltd.org/etd/uwo/oai:uwo.scholaris.ca:20.500.14721/35877","repository":{"repo_id":"uwo","name":"Western University","base_url":"https://uwo.scholaris.ca/server/oai/request"},"display":{"title":"Hardware Implementations for Symmetric Key Cryptosystems","abstract":"The utilization of global communications network for supporting new electronic applications is growing. Many applications provided over the global communications network involve exchange of security-sensitive information between different entities. Often, communicating entities are located at different locations around the globe. This demands deployment of certain mechanisms for providing secure communications channels between these entities. For this purpose, cryptographic algorithms are used by many of today's electronic applications to maintain security. Cryptographic algorithms provide set of primitives for achieving different security goals such as: confidentiality, data integrity, authenticity, and non-repudiation. In general, two main categories of cryptographic algorithms can be used to accomplish any of these security goals, namely, asymmetric key algorithms and symmetric key algorithms. The security of asymmetric key algorithms is based on the hardness of the underlying computational problems, which usually require large overhead of space and time complexities. On the other hand, the security of symmetric key algorithms is based on non-linear transformations and permutations, which provide efficient implementations compared to the asymmetric key ones. Therefore, it is common to use asymmetric key algorithms for key exchange, while symmetric key counterparts are deployed in securing the communications sessions. This thesis focuses on finding efficient hardware implementations for symmetric key cryptosystems targeting mobile communications and resource constrained applications. First, efficient lightweight hardware implementations of two members of the Welch-Gong (WG) family of stream ciphers, the WG$left(29,11right)$ and WG-$16$, are considered for the mobile communications domain. Optimizations in the WG$left(29,11right)$ stream cipher are considered when the $GFleft(2^{29}right)$ elements are represented in either the Optimal normal basis type-II (ONB-II) or the Polynomial basis (PB). For WG-$16$, optimizations are considered only for PB representations of the $GFleft(2^{16}right)$ elements. In this regard, optimizations for both ciphers are accomplished mainly at the arithmetic level through reducing the number of field multipliers, based on novel trace properties. In addition, other optimization techniques such as serialization and pipelining, are also considered. After this, the thesis explores efficient hardware implementations for digit-level multiplication over binary extension fields $GFleft(2^{m}right)$. Efficient digit-level $GFleft(2^{m}right)$ multiplications are advantageous for ultra-lightweight implementations, not only in symmetric key algorithms, but also in asymmetric key algorithms. The thesis introduces new architectures for digit-level $GFleft(2^{m}right)$ multipliers considering the Gaussian normal basis (GNB) and PB representations of the field elements. The new digit-level $GFleft(2^{m}right)$ single multipliers do not require loading of the two input field elements in advance to computations. This feature results in high throughput fast multiplication in resource constrained applications with limited capacity of input data-paths. The new digit-level $GFleft(2^{m}right)$ single multipliers are considered for both the GNB and PB. In addition, for the GNB representation, new architectures for digit-level $GFleft(2^{m}right)$ hybrid-double and hybrid-triple multipliers are introduced. The new digit-level $GFleft(2^{m}right)$ hybrid-double and hybrid-triple GNB multipliers, respectively, accomplish the multiplication of three and four field elements using the latency required for multiplying two field elements. Furthermore, a new hardware architecture for the eight-ary exponentiation scheme is proposed by utilizing the new digit-level $GFleft(2^{m}right)$ hybrid-triple GNB multipliers.","abstract_html":"The utilization of global communications network for supporting new electronic applications is growing. Many applications provided over the global communications network involve exchange of security-sensitive information between different entities. Often, communicating entities are located at different locations around the globe. This demands deployment of certain mechanisms for providing secure communications channels between these entities. For this purpose, cryptographic algorithms are used by many of today&#x27;s electronic applications to maintain security. Cryptographic algorithms provide set of primitives for achieving different security goals such as: confidentiality, data integrity, authenticity, and non-repudiation. In general, two main categories of cryptographic algorithms can be used to accomplish any of these security goals, namely, asymmetric key algorithms and symmetric key algorithms. The security of asymmetric key algorithms is based on the hardness of the underlying computational problems, which usually require large overhead of space and time complexities. On the other hand, the security of symmetric key algorithms is based on non-linear transformations and permutations, which provide efficient implementations compared to the asymmetric key ones. Therefore, it is common to use asymmetric key algorithms for key exchange, while symmetric key counterparts are deployed in securing the communications sessions. This thesis focuses on finding efficient hardware implementations for symmetric key cryptosystems targeting mobile communications and resource constrained applications. First, efficient lightweight hardware implementations of two members of the Welch-Gong (WG) family of stream ciphers, the WG$left(29,11right)$ and WG-$16$, are considered for the mobile communications domain. Optimizations in the WG$left(29,11right)$ stream cipher are considered when the <span class=\"etd-inline-math\">GFleft(2<sup>29</sup>right)</span> elements are represented in either the Optimal normal basis type-II (ONB-II) or the Polynomial basis (PB). For WG-$16$, optimizations are considered only for PB representations of the <span class=\"etd-inline-math\">GFleft(2<sup>16</sup>right)</span> elements. In this regard, optimizations for both ciphers are accomplished mainly at the arithmetic level through reducing the number of field multipliers, based on novel trace properties. In addition, other optimization techniques such as serialization and pipelining, are also considered. After this, the thesis explores efficient hardware implementations for digit-level multiplication over binary extension fields <span class=\"etd-inline-math\">GFleft(2<sup>m</sup>right)</span>. Efficient digit-level <span class=\"etd-inline-math\">GFleft(2<sup>m</sup>right)</span> multiplications are advantageous for ultra-lightweight implementations, not only in symmetric key algorithms, but also in asymmetric key algorithms. The thesis introduces new architectures for digit-level <span class=\"etd-inline-math\">GFleft(2<sup>m</sup>right)</span> multipliers considering the Gaussian normal basis (GNB) and PB representations of the field elements. The new digit-level <span class=\"etd-inline-math\">GFleft(2<sup>m</sup>right)</span> single multipliers do not require loading of the two input field elements in advance to computations. This feature results in high throughput fast multiplication in resource constrained applications with limited capacity of input data-paths. The new digit-level <span class=\"etd-inline-math\">GFleft(2<sup>m</sup>right)</span> single multipliers are considered for both the GNB and PB. In addition, for the GNB representation, new architectures for digit-level <span class=\"etd-inline-math\">GFleft(2<sup>m</sup>right)</span> hybrid-double and hybrid-triple multipliers are introduced. The new digit-level <span class=\"etd-inline-math\">GFleft(2<sup>m</sup>right)</span> hybrid-double and hybrid-triple GNB multipliers, respectively, accomplish the multiplication of three and four field elements using the latency required for multiplying two field elements. Furthermore, a new hardware architecture for the eight-ary exponentiation scheme is proposed by utilizing the new digit-level <span class=\"etd-inline-math\">GFleft(2<sup>m</sup>right)</span> hybrid-triple GNB multipliers.","abstract_has_math":true,"creators":["El-Razouk, Hayssam"],"institution":"The University of Western Ontario","degree_name":"Ph D","degree_level":null,"degree_discipline":"Electrical and Computer Engineering","degree_department":null,"school":null,"contributors":[],"advisors":["Reyhani-Masoleh, Arash"],"committee_chairs":[],"committee_members":[],"year":2015,"date_issued":"2015-06-05","date_published":"2015-06-05","updated_at":"2026-07-27T21:56:18Z","subjects":["Digit-Level Multipliers","Finite Fields","Gaussian Normal Basis","Polynomial Basis","Pseudo Random Key Generators","WG Transformation"],"languages":["en_ca"],"rights":[],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"https://hdl.handle.net/20.500.14721/35877","outbound_label":"Handle","outbound_source":"dc:identifier.uri"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor.advisor","label":"Advisor","values":["Reyhani-Masoleh, Arash"]},{"key":"dc:creator","label":"Author","values":["El-Razouk, Hayssam"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date.accessioned","label":"Dc Date Accessioned","values":["2025-07-10T20:43:14Z"]},{"key":"dc:date.available","label":"Dc Date Available","values":["2025-07-10T20:43:14Z"]},{"key":"dc:date.issued","label":"Date","values":["2015-06-05"]},{"key":"dc:publisher","label":"Institution","values":["The University of Western Ontario"]},{"key":"dc:type","label":"Dc Type","values":["thesis"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical and Computer Engineering"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Ph D"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Digit-Level Multipliers","Finite Fields","Gaussian Normal Basis","Polynomial Basis","Pseudo Random Key Generators","WG Transformation"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language.iso","label":"Language (ISO)","values":["en_ca"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier.uri","label":"Identifier URI","values":["https://hdl.handle.net/20.500.14721/35877"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["The thesis cover page in the PDF document includes references to Western University’s previous institutional repository platform, known as Scholarship@Western, and links to that platform (beginning with ir.lib.uwo.ca). In citing or referring to this thesis, use the DOI or handle from this page instead. Sample citation: Author name, \"Thesis title.\" (Year). Western University Open Repository. https://doi.org/10.71858/123456."]},{"key":"dc:description.abstract","label":"Abstract","values":["The utilization of global communications network for supporting new electronic applications is growing. Many applications provided over the global communications network involve exchange of security-sensitive information between different entities. Often, communicating entities are located at different locations around the globe. This demands deployment of certain mechanisms for providing secure communications channels between these entities. For this purpose, cryptographic algorithms are used by many of today's electronic applications to maintain security. Cryptographic algorithms provide set of primitives for achieving different security goals such as: confidentiality, data integrity, authenticity, and non-repudiation. In general, two main categories of cryptographic algorithms can be used to accomplish any of these security goals, namely, asymmetric key algorithms and symmetric key algorithms. The security of asymmetric key algorithms is based on the hardness of the underlying computational problems, which usually require large overhead of space and time complexities. On the other hand, the security of symmetric key algorithms is based on non-linear transformations and permutations, which provide efficient implementations compared to the asymmetric key ones. Therefore, it is common to use asymmetric key algorithms for key exchange, while symmetric key counterparts are deployed in securing the communications sessions. This thesis focuses on finding efficient hardware implementations for symmetric key cryptosystems targeting mobile communications and resource constrained applications. First, efficient lightweight hardware implementations of two members of the Welch-Gong (WG) family of stream ciphers, the WG$left(29,11right)$ and WG-$16$, are considered for the mobile communications domain. Optimizations in the WG$left(29,11right)$ stream cipher are considered when the $GFleft(2^{29}right)$ elements are represented in either the Optimal normal basis type-II (ONB-II) or the Polynomial basis (PB). For WG-$16$, optimizations are considered only for PB representations of the $GFleft(2^{16}right)$ elements. In this regard, optimizations for both ciphers are accomplished mainly at the arithmetic level through reducing the number of field multipliers, based on novel trace properties. In addition, other optimization techniques such as serialization and pipelining, are also considered. After this, the thesis explores efficient hardware implementations for digit-level multiplication over binary extension fields $GFleft(2^{m}right)$. Efficient digit-level $GFleft(2^{m}right)$ multiplications are advantageous for ultra-lightweight implementations, not only in symmetric key algorithms, but also in asymmetric key algorithms. The thesis introduces new architectures for digit-level $GFleft(2^{m}right)$ multipliers considering the Gaussian normal basis (GNB) and PB representations of the field elements. The new digit-level $GFleft(2^{m}right)$ single multipliers do not require loading of the two input field elements in advance to computations. This feature results in high throughput fast multiplication in resource constrained applications with limited capacity of input data-paths. The new digit-level $GFleft(2^{m}right)$ single multipliers are considered for both the GNB and PB. In addition, for the GNB representation, new architectures for digit-level $GFleft(2^{m}right)$ hybrid-double and hybrid-triple multipliers are introduced. The new digit-level $GFleft(2^{m}right)$ hybrid-double and hybrid-triple GNB multipliers, respectively, accomplish the multiplication of three and four field elements using the latency required for multiplying two field elements. Furthermore, a new hardware architecture for the eight-ary exponentiation scheme is proposed by utilizing the new digit-level $GFleft(2^{m}right)$ hybrid-triple GNB multipliers."]},{"key":"dc:title","label":"Title","values":["Hardware Implementations for Symmetric Key Cryptosystems"]}]}],"canonical_facts":{"dc:contributor.advisor":["Reyhani-Masoleh, Arash"],"dc:creator":["El-Razouk, Hayssam"],"dc:date.accessioned":["2025-07-10T20:43:14Z"],"dc:date.available":["2025-07-10T20:43:14Z"],"dc:date.issued":["2015-06-05"],"dc:description":["The thesis cover page in the PDF document includes references to Western University’s previous institutional repository platform, known as Scholarship@Western, and links to that platform (beginning with ir.lib.uwo.ca). In citing or referring to this thesis, use the DOI or handle from this page instead. Sample citation: Author name, \"Thesis title.\" (Year). Western University Open Repository. https://doi.org/10.71858/123456."],"dc:description.abstract":["The utilization of global communications network for supporting new electronic applications is growing. Many applications provided over the global communications network involve exchange of security-sensitive information between different entities. Often, communicating entities are located at different locations around the globe. This demands deployment of certain mechanisms for providing secure communications channels between these entities. For this purpose, cryptographic algorithms are used by many of today's electronic applications to maintain security. Cryptographic algorithms provide set of primitives for achieving different security goals such as: confidentiality, data integrity, authenticity, and non-repudiation. In general, two main categories of cryptographic algorithms can be used to accomplish any of these security goals, namely, asymmetric key algorithms and symmetric key algorithms. The security of asymmetric key algorithms is based on the hardness of the underlying computational problems, which usually require large overhead of space and time complexities. On the other hand, the security of symmetric key algorithms is based on non-linear transformations and permutations, which provide efficient implementations compared to the asymmetric key ones. Therefore, it is common to use asymmetric key algorithms for key exchange, while symmetric key counterparts are deployed in securing the communications sessions. This thesis focuses on finding efficient hardware implementations for symmetric key cryptosystems targeting mobile communications and resource constrained applications. First, efficient lightweight hardware implementations of two members of the Welch-Gong (WG) family of stream ciphers, the WG$left(29,11right)$ and WG-$16$, are considered for the mobile communications domain. Optimizations in the WG$left(29,11right)$ stream cipher are considered when the $GFleft(2^{29}right)$ elements are represented in either the Optimal normal basis type-II (ONB-II) or the Polynomial basis (PB). For WG-$16$, optimizations are considered only for PB representations of the $GFleft(2^{16}right)$ elements. In this regard, optimizations for both ciphers are accomplished mainly at the arithmetic level through reducing the number of field multipliers, based on novel trace properties. In addition, other optimization techniques such as serialization and pipelining, are also considered. After this, the thesis explores efficient hardware implementations for digit-level multiplication over binary extension fields $GFleft(2^{m}right)$. Efficient digit-level $GFleft(2^{m}right)$ multiplications are advantageous for ultra-lightweight implementations, not only in symmetric key algorithms, but also in asymmetric key algorithms. The thesis introduces new architectures for digit-level $GFleft(2^{m}right)$ multipliers considering the Gaussian normal basis (GNB) and PB representations of the field elements. The new digit-level $GFleft(2^{m}right)$ single multipliers do not require loading of the two input field elements in advance to computations. This feature results in high throughput fast multiplication in resource constrained applications with limited capacity of input data-paths. The new digit-level $GFleft(2^{m}right)$ single multipliers are considered for both the GNB and PB. In addition, for the GNB representation, new architectures for digit-level $GFleft(2^{m}right)$ hybrid-double and hybrid-triple multipliers are introduced. The new digit-level $GFleft(2^{m}right)$ hybrid-double and hybrid-triple GNB multipliers, respectively, accomplish the multiplication of three and four field elements using the latency required for multiplying two field elements. Furthermore, a new hardware architecture for the eight-ary exponentiation scheme is proposed by utilizing the new digit-level $GFleft(2^{m}right)$ hybrid-triple GNB multipliers."],"dc:identifier.uri":["https://hdl.handle.net/20.500.14721/35877"],"dc:language.iso":["en_ca"],"dc:publisher":["The University of Western Ontario"],"dc:subject":["Digit-Level Multipliers","Finite Fields","Gaussian Normal Basis","Polynomial Basis","Pseudo Random Key Generators","WG Transformation"],"dc:title":["Hardware Implementations for Symmetric Key Cryptosystems"],"dc:type":["thesis"],"thesis:degree_discipline":["Electrical and Computer Engineering"],"thesis:degree_name":["Ph D"]},"updated_at":"2026-07-27T21:56:18Z"}