{"id":{"repo_id":"uts","oai_identifier":"oai:opus.lib.uts.edu.au:10453/190600"},"canonical_url":"https://search.dev.ndltd.org/etd/uts/oai:opus.lib.uts.edu.au:10453/190600","repository":{"repo_id":"uts","name":"University of Technology Sydney","base_url":"https://opus.lib.uts.edu.au/oai/request"},"display":{"title":"Design of millimetre-wave input-reflectionless amplifiers in 45nm CMOS-SOI Technology","abstract":"In this thesis, a proposed method to minimize the impacts of out-of-band RF blocks using a novel circuit design technique is proposed for millimeter-wave amplifiers. Using this technique for amplifier design allows it to attain an input-reflectionless behavior at not only the passband but also the stopband. For proof-of-concept, three input-reflectionless amplifiers are designed and implemented using 45-nm silicon-on-insulator (SOI) CMOS technology. The first design is a single-stage narrowband amplifier. The DC-power consumption of the designed amplifier is 5.3 mW. It has a peak gain of 5.3 dB at 31 GHz. The input-power-matching levels of the designed amplifier are better than 10 dB from DC to 50 GHz. The second design is a two-stage amplifier, is a two-stage narrowband amplifier which builds upon the design technique and extend it to multi-stage input-reflectionless amplifiers. The DC-power consumption of the designed amplifier is 10.35 mW. It has a peak gain of 18.5 dB at 35 GHz. The input-power-matching level is smaller than -10 dB from DC to 50 GHz. Finally, the design technique is also applied to a wideband amplifier design. The 3-dB bandwidth of 21 - 42 GHz is achieved, with a peak gain of 14 dB.","abstract_html":"In this thesis, a proposed method to minimize the impacts of out-of-band RF blocks using a novel circuit design technique is proposed for millimeter-wave amplifiers. Using this technique for amplifier design allows it to attain an input-reflectionless behavior at not only the passband but also the stopband. For proof-of-concept, three input-reflectionless amplifiers are designed and implemented using 45-nm silicon-on-insulator (SOI) CMOS technology. The first design is a single-stage narrowband amplifier. The DC-power consumption of the designed amplifier is 5.3 mW. It has a peak gain of 5.3 dB at 31 GHz. The input-power-matching levels of the designed amplifier are better than 10 dB from DC to 50 GHz. The second design is a two-stage amplifier, is a two-stage narrowband amplifier which builds upon the design technique and extend it to multi-stage input-reflectionless amplifiers. The DC-power consumption of the designed amplifier is 10.35 mW. It has a peak gain of 18.5 dB at 35 GHz. The input-power-matching level is smaller than -10 dB from DC to 50 GHz. Finally, the design technique is also applied to a wideband amplifier design. The 3-dB bandwidth of 21 - 42 GHz is achieved, with a peak gain of 14 dB.","abstract_has_math":false,"creators":["Ang, Jim Darrell"],"institution":null,"degree_name":null,"degree_level":null,"degree_discipline":null,"degree_department":null,"school":null,"contributors":[],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2025,"date_issued":"2025","date_published":"2025","updated_at":"2026-07-24T06:32:12Z","subjects":[],"languages":["en_US"],"rights":["info:eu-repo/semantics/embargoedAccess","The author owns the copyright in this thesis including all reproduction and reuse rights for the work. The work may not be altered without the permission of the copyright owner. Attribution is essential when quoting or paraphrasing from this thesis.","© 2025 Jim Darrell Ang","au.edu.uts.lib/nph"],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"http://hdl.handle.net/10453/190600","outbound_label":"Handle","outbound_source":"dc:identifier.uri"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:creator","label":"Author","values":["Ang, Jim Darrell"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date.accessioned","label":"Dc Date Accessioned","values":["2025-11-03T04:19:06Z"]},{"key":"dc:date.available","label":"Dc Date Available","values":["2025-11-03T04:19:06Z"]},{"key":"dc:date.issued","label":"Date","values":["2025"]},{"key":"dc:type","label":"Dc Type","values":["Thesis"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language.iso","label":"Language (ISO)","values":["en_US"]},{"key":"dc:rights","label":"Dc Rights","values":["info:eu-repo/semantics/embargoedAccess","The author owns the copyright in this thesis including all reproduction and reuse rights for the work. The work may not be altered without the permission of the copyright owner. Attribution is essential when quoting or paraphrasing from this thesis.","© 2025 Jim Darrell Ang","au.edu.uts.lib/nph"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier.uri","label":"Identifier URI","values":["http://hdl.handle.net/10453/190600"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["University of Technology Sydney. Faculty of Engineering and Information Technology."]},{"key":"dc:description.abstract","label":"Abstract","values":["In this thesis, a proposed method to minimize the impacts of out-of-band RF blocks using a novel circuit design technique is proposed for millimeter-wave amplifiers. Using this technique for amplifier design allows it to attain an input-reflectionless behavior at not only the passband but also the stopband. For proof-of-concept, three input-reflectionless amplifiers are designed and implemented using 45-nm silicon-on-insulator (SOI) CMOS technology. The first design is a single-stage narrowband amplifier. The DC-power consumption of the designed amplifier is 5.3 mW. It has a peak gain of 5.3 dB at 31 GHz. The input-power-matching levels of the designed amplifier are better than 10 dB from DC to 50 GHz. The second design is a two-stage amplifier, is a two-stage narrowband amplifier which builds upon the design technique and extend it to multi-stage input-reflectionless amplifiers. The DC-power consumption of the designed amplifier is 10.35 mW. It has a peak gain of 18.5 dB at 35 GHz. The input-power-matching level is smaller than -10 dB from DC to 50 GHz. Finally, the design technique is also applied to a wideband amplifier design. The 3-dB bandwidth of 21 - 42 GHz is achieved, with a peak gain of 14 dB."]},{"key":"dc:format","label":"Dc Format","values":["Thesis (PhD)"]},{"key":"dc:title","label":"Title","values":["Design of millimetre-wave input-reflectionless amplifiers in 45nm CMOS-SOI Technology"]}]}],"canonical_facts":{"dc:creator":["Ang, Jim Darrell"],"dc:date.accessioned":["2025-11-03T04:19:06Z"],"dc:date.available":["2025-11-03T04:19:06Z"],"dc:date.issued":["2025"],"dc:description":["University of Technology Sydney. Faculty of Engineering and Information Technology."],"dc:description.abstract":["In this thesis, a proposed method to minimize the impacts of out-of-band RF blocks using a novel circuit design technique is proposed for millimeter-wave amplifiers. Using this technique for amplifier design allows it to attain an input-reflectionless behavior at not only the passband but also the stopband. For proof-of-concept, three input-reflectionless amplifiers are designed and implemented using 45-nm silicon-on-insulator (SOI) CMOS technology. The first design is a single-stage narrowband amplifier. The DC-power consumption of the designed amplifier is 5.3 mW. It has a peak gain of 5.3 dB at 31 GHz. The input-power-matching levels of the designed amplifier are better than 10 dB from DC to 50 GHz. The second design is a two-stage amplifier, is a two-stage narrowband amplifier which builds upon the design technique and extend it to multi-stage input-reflectionless amplifiers. The DC-power consumption of the designed amplifier is 10.35 mW. It has a peak gain of 18.5 dB at 35 GHz. The input-power-matching level is smaller than -10 dB from DC to 50 GHz. Finally, the design technique is also applied to a wideband amplifier design. The 3-dB bandwidth of 21 - 42 GHz is achieved, with a peak gain of 14 dB."],"dc:format":["Thesis (PhD)"],"dc:identifier.uri":["http://hdl.handle.net/10453/190600"],"dc:language.iso":["en_US"],"dc:rights":["info:eu-repo/semantics/embargoedAccess","The author owns the copyright in this thesis including all reproduction and reuse rights for the work. The work may not be altered without the permission of the copyright owner. Attribution is essential when quoting or paraphrasing from this thesis.","© 2025 Jim Darrell Ang","au.edu.uts.lib/nph"],"dc:title":["Design of millimetre-wave input-reflectionless amplifiers in 45nm CMOS-SOI Technology"],"dc:type":["Thesis"]},"updated_at":"2026-07-24T06:32:12Z"}