Design of low power high speed digital vedic multiplier using 13T hybrid full adder

The increment of demand for battery operated portable devices has laid emphasis on the development of low power multiplier and high performance systems. Multiplier is omnipresent in most common circuits; and adders act as the main block for the multiplier to operate. Performance of full adder had direct impact in all arithmetic circuits. In this thesis, a 4x4 bit Vedic multiplier has been successfully designed using the combination of Urdhva Triyakbyam Sutras and 13 transistors (13T) hybrid full adder (HFA). The Urdhva Triyakbyam algorithm satisfies the requirement of a fast multiplication operation which reduced large number of partial products when compared to others. Meanwhile the HFA is a new designed adder which is proposed in this thesis is able to produce full output voltage swing output using low power consumption (18.97 μW) and least delay (46.8 ps). The multiplier is designed and simulated at the transistor level circuit and the layout circuit using Synopsys EDA Tools with Process Design Kit (PDK) of 90 nm Complementary Metal Oxide Semiconductor (CMOS) technology. With a 1 V voltage supply associated with load capacitance of 0.1 pF, this 4x4 bit Vedic multiplier is able to produce an output with the power consumption of 0.2015 mW, delay of 376 ps and a compact area which only consumed 3100 μm2 (54.39 μm x 57.00 μm). The number of transistor for this multiplier is only 356 transistors. Novelty SUM circuit that newly designed in this project had a huge contribution in reducing the transistors count from 6T to 4T. With the reduction of transistors count in this circuit, the overall power consumption, the delay time and the layout had been reduced.

Name dc:type.qualificationname

mphil

Level dc:type.qualificationlevel

masters

Grantor dc:publisher.institution

Universiti Tun Hussein Onn Malaysia

Year dc:date.issued

2018

Author dc:creator

• Lee, Shing Jie

• QA76 Computer software

Language dc:language

en