{"id":{"repo_id":"utc","oai_identifier":"oai:scholar.utc.edu:theses-1727"},"canonical_url":"https://search.dev.ndltd.org/etd/utc/oai:scholar.utc.edu:theses-1727","repository":{"repo_id":"utc","name":"University of Tennessee - Chattanooga","base_url":"https://scholar.utc.edu/do/oai/"},"display":{"title":"A method for characterization of single-event latchup technologies as a function of geometric variation","abstract":"Complementary metal-oxide-semiconductor (CMOS) technology is the dominant integrated circuit (IC) technology in modern electronics systems. As CMOS comprises of p-channel and n-channel transistors, there are parasitic PNPN paths that act as cross-coupled bipolar transistors capable of creating low-impedance paths between the power supply rails known as the “latchup” state. Latchup is destructive and requires a power cycle to restore operation. Latchup can be stimulated by ionizing radiation such as a high-energy proton or heavy-ions from deep space, resulting in a significant vulnerability in CMOS space systems. The sensitivity of an IC to single-event latchup (SEL) depends on various process parameters as well as design geometry. This work presents a method for the characterization of the geometric effects of CMOS layout on SEL. The dominant geometric contributors to the overall SEL sensitivity include: (1) substrate contact-to-source spacing (PWNS), (2) well contact-to-source spacing (NWPS), and (3) source-to-source spacing (SS).","abstract_html":"Complementary metal-oxide-semiconductor (CMOS) technology is the dominant integrated circuit (IC) technology in modern electronics systems. As CMOS comprises of p-channel and n-channel transistors, there are parasitic PNPN paths that act as cross-coupled bipolar transistors capable of creating low-impedance paths between the power supply rails known as the “latchup” state. Latchup is destructive and requires a power cycle to restore operation. Latchup can be stimulated by ionizing radiation such as a high-energy proton or heavy-ions from deep space, resulting in a significant vulnerability in CMOS space systems. The sensitivity of an IC to single-event latchup (SEL) depends on various process parameters as well as design geometry. This work presents a method for the characterization of the geometric effects of CMOS layout on SEL. The dominant geometric contributors to the overall SEL sensitivity include: (1) substrate contact-to-source spacing (PWNS), (2) well contact-to-source spacing (NWPS), and (3) source-to-source spacing (SS).","abstract_has_math":false,"creators":["Joplin, Matt"],"institution":"University of Tennessee at Chattanooga","degree_name":null,"degree_level":null,"degree_discipline":null,"degree_department":null,"school":null,"contributors":["Loveless, T. Daniel","Ofoli, Abdul R.","College of Engineering and Computer Science"],"advisors":[],"committee_chairs":[],"committee_members":[],"year":null,"date_issued":"","date_published":null,"updated_at":"2026-07-24T05:46:51Z","subjects":["Metal oxide semiconductors, Complementary -- Design and construction"],"languages":["English","eng"],"rights":[],"rights_urls":["https://rightsstatements.org/page/InC/1.0/?language=en"],"identifier_entries":[]},"links":{"outbound_url":"https://scholar.utc.edu/theses/567","outbound_label":"Repository record","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Loveless, T. Daniel","Ofoli, Abdul R.","College of Engineering and Computer Science"]},{"key":"dc:creator","label":"Author","values":["Joplin, Matt"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2018-08-01T07:00:00Z"]},{"key":"dc:publisher","label":"Institution","values":["University of Tennessee at Chattanooga","Chattanooga (Tenn.)"]},{"key":"dc:relation","label":"Dc Relation","values":["Masters Theses and Doctoral Dissertations"]},{"key":"dc:type","label":"Dc Type","values":["Masters theses","Text"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Metal oxide semiconductors, Complementary -- Design and construction"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["English","eng"]},{"key":"dc:rights","label":"Dc Rights","values":["https://rightsstatements.org/page/InC/1.0/?language=en"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["https://scholar.utc.edu/theses/567"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["Dept. of Electrical Engineering","M. S.; A thesis submitted to the faculty of the University of Tennessee at Chattanooga in partial fulfillment of the requirements of the degree of Master of Science."]},{"key":"dc:description.abstract","label":"Abstract","values":["Complementary metal-oxide-semiconductor (CMOS) technology is the dominant integrated circuit (IC) technology in modern electronics systems. As CMOS comprises of p-channel and n-channel transistors, there are parasitic PNPN paths that act as cross-coupled bipolar transistors capable of creating low-impedance paths between the power supply rails known as the “latchup” state. Latchup is destructive and requires a power cycle to restore operation. Latchup can be stimulated by ionizing radiation such as a high-energy proton or heavy-ions from deep space, resulting in a significant vulnerability in CMOS space systems. The sensitivity of an IC to single-event latchup (SEL) depends on various process parameters as well as design geometry. This work presents a method for the characterization of the geometric effects of CMOS layout on SEL. The dominant geometric contributors to the overall SEL sensitivity include: (1) substrate contact-to-source spacing (PWNS), (2) well contact-to-source spacing (NWPS), and (3) source-to-source spacing (SS)."]},{"key":"dc:title","label":"Title","values":["A method for characterization of single-event latchup technologies as a function of geometric variation"]}]}],"canonical_facts":{"dc:contributor":["Loveless, T. Daniel","Ofoli, Abdul R.","College of Engineering and Computer Science"],"dc:creator":["Joplin, Matt"],"dc:date":["2018-08-01T07:00:00Z"],"dc:description":["Dept. of Electrical Engineering","M. S.; A thesis submitted to the faculty of the University of Tennessee at Chattanooga in partial fulfillment of the requirements of the degree of Master of Science."],"dc:description.abstract":["Complementary metal-oxide-semiconductor (CMOS) technology is the dominant integrated circuit (IC) technology in modern electronics systems. As CMOS comprises of p-channel and n-channel transistors, there are parasitic PNPN paths that act as cross-coupled bipolar transistors capable of creating low-impedance paths between the power supply rails known as the “latchup” state. Latchup is destructive and requires a power cycle to restore operation. Latchup can be stimulated by ionizing radiation such as a high-energy proton or heavy-ions from deep space, resulting in a significant vulnerability in CMOS space systems. The sensitivity of an IC to single-event latchup (SEL) depends on various process parameters as well as design geometry. This work presents a method for the characterization of the geometric effects of CMOS layout on SEL. The dominant geometric contributors to the overall SEL sensitivity include: (1) substrate contact-to-source spacing (PWNS), (2) well contact-to-source spacing (NWPS), and (3) source-to-source spacing (SS)."],"dc:identifier":["https://scholar.utc.edu/theses/567"],"dc:language":["English","eng"],"dc:publisher":["University of Tennessee at Chattanooga","Chattanooga (Tenn.)"],"dc:relation":["Masters Theses and Doctoral Dissertations"],"dc:rights":["https://rightsstatements.org/page/InC/1.0/?language=en"],"dc:subject":["Metal oxide semiconductors, Complementary -- Design and construction"],"dc:title":["A method for characterization of single-event latchup technologies as a function of geometric variation"],"dc:type":["Masters theses","Text"]},"updated_at":"2026-07-24T05:46:51Z"}