A System-on-Programmable-Chip Approach for MIMO Lattice Decoder

The past decade has shown distinct advances in the theory of multiple input multi output techniques for wireless communication systems. Now, the time has come to demonstrate this progress in terms of applications. This thesis introduces implementation of Schnorr- Euchner strategy based decoding algorithm applied on Altera system-on-chip (Stratix EP1S10F780C6) with Nios embedded processor. The lattice decoder is developed on FPGA using VHDL. The preprocessing part of algorithm is targeted for Nios embedded processor using C language. A controller is also designed to interface and communicate between the Nios embedded processor and lattice decoder.

Name thesis:degree_name

M.S.

Level thesis:degree_level

Thesis

Discipline thesis:degree_discipline

Electrical Engineering

Year

2004

Author dc:creator

• Patel, Vipul Hiralal

Contributors dc:contributor

• Huang, Xinming
• Charalampidis, Dimitrios
• Ma, Jing

• MIMO
• Lattice Decoder
• System-on-Progammable-Chip

Repository record dc:identifier

https://scholarworks.uno.edu/td/192

OAI identifier oai:identifier

oai:scholarworks.uno.edu:td-1196