{"id":{"repo_id":"unm","oai_identifier":"oai:digitalrepository.unm.edu:ece_etds-1167"},"canonical_url":"https://search.dev.ndltd.org/etd/unm/oai:digitalrepository.unm.edu:ece_etds-1167","repository":{"repo_id":"unm","name":"University of New Mexico","base_url":"https://digitalrepository.unm.edu/do/oai/"},"display":{"title":"Single event upset hardened CMOS combinational logic and clock buffer design","abstract":"A radiation strike on semiconductor device may lead to charge collection, which may manifest as a wrong logic level causing failure. Soft errors or Single Event Upsets (SEU) caused by radiation strikes are one of the main failure modes in a VLSI circuit. Previous work predicts that soft error rate may dominate the failure rate in VLSI circuit compared to all other failure modes put together. The issue of single event upsets (SEU) need to be addressed such that the failure rate of the chips dues to SEU is in the acceptable range. Memory circuits are designed to be error free with the help of error correction codes. Technology scaling is driving up the SEU rate of combinational logic and it is predicted that the soft error rate (SER) of combinational logic may dominate the SER of unpro-tected memory by the year 2011. Hence a robust combinational logic methodology must be designed for SEU hardening. Recent studies have also shown that clock distribution network is becoming increasingly vulnerable to radiation strike due to reduced capaci-tance at the clock leaf node. A strike on clock leaf node may propagate to many flip-flops increasing the system SER considerably. In this thesis we propose a novel method to improve the SER of the circuit by filtering single event upsets in the combinational logic and clock distribution network. Our ap-proach results in minimal circuit overhead and also requires minimal effort by the de-signer to implement the proposed method. In this thesis we focus on preventing the propagation of SEU rather than eliminating the SEU on each sensitive gate.","abstract_html":"A radiation strike on semiconductor device may lead to charge collection, which may manifest as a wrong logic level causing failure. Soft errors or Single Event Upsets (SEU) caused by radiation strikes are one of the main failure modes in a VLSI circuit. Previous work predicts that soft error rate may dominate the failure rate in VLSI circuit compared to all other failure modes put together. The issue of single event upsets (SEU) need to be addressed such that the failure rate of the chips dues to SEU is in the acceptable range. Memory circuits are designed to be error free with the help of error correction codes. Technology scaling is driving up the SEU rate of combinational logic and it is predicted that the soft error rate (SER) of combinational logic may dominate the SER of unpro-tected memory by the year 2011. Hence a robust combinational logic methodology must be designed for SEU hardening. Recent studies have also shown that clock distribution network is becoming increasingly vulnerable to radiation strike due to reduced capaci-tance at the clock leaf node. A strike on clock leaf node may propagate to many flip-flops increasing the system SER considerably. In this thesis we propose a novel method to improve the SER of the circuit by filtering single event upsets in the combinational logic and clock distribution network. Our ap-proach results in minimal circuit overhead and also requires minimal effort by the de-signer to implement the proposed method. In this thesis we focus on preventing the propagation of SEU rather than eliminating the SEU on each sensitive gate.","abstract_has_math":false,"creators":["Mallajosyula, Aahlad"],"institution":null,"degree_name":"Electrical Engineering","degree_level":"Thesis","degree_discipline":"Electrical and Computer Engineering","degree_department":null,"school":null,"contributors":["Zarkesh-Ha, Payman","Krishna, Sanjay","Graham, Edward Jr"],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2009,"date_issued":"2009-01-29T08:00:00Z","date_published":"2009-01-29T08:00:00Z","updated_at":"2026-07-24T05:27:19Z","subjects":["Metal oxide semiconductors","Complementary"],"languages":["English"],"rights":[],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"https://digitalrepository.unm.edu/ece_etds/168","outbound_label":"Repository record","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Zarkesh-Ha, Payman","Krishna, Sanjay","Graham, Edward Jr"]},{"key":"dc:creator","label":"Author","values":["Mallajosyula, Aahlad"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical and Computer Engineering"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Thesis","Masters"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Electrical Engineering"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Metal oxide semiconductors","Complementary"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["English"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["https://digitalrepository.unm.edu/ece_etds/168"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description.abstract","label":"Abstract","values":["A radiation strike on semiconductor device may lead to charge collection, which may manifest as a wrong logic level causing failure. Soft errors or Single Event Upsets (SEU) caused by radiation strikes are one of the main failure modes in a VLSI circuit. Previous work predicts that soft error rate may dominate the failure rate in VLSI circuit compared to all other failure modes put together. The issue of single event upsets (SEU) need to be addressed such that the failure rate of the chips dues to SEU is in the acceptable range. Memory circuits are designed to be error free with the help of error correction codes. Technology scaling is driving up the SEU rate of combinational logic and it is predicted that the soft error rate (SER) of combinational logic may dominate the SER of unpro-tected memory by the year 2011. Hence a robust combinational logic methodology must be designed for SEU hardening. Recent studies have also shown that clock distribution network is becoming increasingly vulnerable to radiation strike due to reduced capaci-tance at the clock leaf node. A strike on clock leaf node may propagate to many flip-flops increasing the system SER considerably. In this thesis we propose a novel method to improve the SER of the circuit by filtering single event upsets in the combinational logic and clock distribution network. Our ap-proach results in minimal circuit overhead and also requires minimal effort by the de-signer to implement the proposed method. In this thesis we focus on preventing the propagation of SEU rather than eliminating the SEU on each sensitive gate."]},{"key":"dc:title","label":"Title","values":["Single event upset hardened CMOS combinational logic and clock buffer design"]}]}],"canonical_facts":{"dc:contributor":["Zarkesh-Ha, Payman","Krishna, Sanjay","Graham, Edward Jr"],"dc:creator":["Mallajosyula, Aahlad"],"dc:description.abstract":["A radiation strike on semiconductor device may lead to charge collection, which may manifest as a wrong logic level causing failure. Soft errors or Single Event Upsets (SEU) caused by radiation strikes are one of the main failure modes in a VLSI circuit. Previous work predicts that soft error rate may dominate the failure rate in VLSI circuit compared to all other failure modes put together. The issue of single event upsets (SEU) need to be addressed such that the failure rate of the chips dues to SEU is in the acceptable range. Memory circuits are designed to be error free with the help of error correction codes. Technology scaling is driving up the SEU rate of combinational logic and it is predicted that the soft error rate (SER) of combinational logic may dominate the SER of unpro-tected memory by the year 2011. Hence a robust combinational logic methodology must be designed for SEU hardening. Recent studies have also shown that clock distribution network is becoming increasingly vulnerable to radiation strike due to reduced capaci-tance at the clock leaf node. A strike on clock leaf node may propagate to many flip-flops increasing the system SER considerably. In this thesis we propose a novel method to improve the SER of the circuit by filtering single event upsets in the combinational logic and clock distribution network. Our ap-proach results in minimal circuit overhead and also requires minimal effort by the de-signer to implement the proposed method. In this thesis we focus on preventing the propagation of SEU rather than eliminating the SEU on each sensitive gate."],"dc:identifier":["https://digitalrepository.unm.edu/ece_etds/168"],"dc:language":["English"],"dc:subject":["Metal oxide semiconductors","Complementary"],"dc:title":["Single event upset hardened CMOS combinational logic and clock buffer design"],"thesis:degree_discipline":["Electrical and Computer Engineering"],"thesis:degree_level":["Thesis","Masters"],"thesis:degree_name":["Electrical Engineering"]},"updated_at":"2026-07-24T05:27:19Z"}