Analog multiply and accumulate FPA readout circuit with digital multiply and sign maintenance

The high bandwidth and power needed to process the data coming from modern high resolution focal plane arrays leads to the necessity for fast and efficient read out and data processing. A system that performs block recognition and image classification with efficiency and low latency is presented. The system is comprised of an analog signal processor that will be integrated into the read out integrated circuit. This enables the capability to read out the focal plane array information and process it completely in the analog domain in a comparably very small amount of operational steps. The steps and techniques of the design flow, including definition of problem, concepts and design of system architecture, simulation of system, and analog lay out practices are covered.

Name thesis:degree_name

Electrical Engineering

Level thesis:degree_level

Thesis

Discipline thesis:degree_discipline

Electrical and Computer Engineering

Year

2012

Author dc:creator

• LeBoeuf, Thomas

Contributors dc:contributor

• Zarkesh-Ha, Payman
• Plusquellic, James
• Graham, Edward

• Signal processing -- Equipment and supplies.
• Image processing -- Equipment and supplies.
• Linear integrated circuits.

Language dc:language

English

Repository record dc:identifier

https://digitalrepository.unm.edu/ece_etds/154

OAI identifier oai:identifier

oai:digitalrepository.unm.edu:ece_etds-1153