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University of New Mexico

Imperfection-Aware Design of CNFET Digital VLSI Circuits

Abstract

dc:description.abstract

<p>Carbon nanotube field-effect transistor (CNFET) is one of the promising candidates as extensions to silicon CMOS devices. The CNFET, which is a 1-D structure with a near-ballistic transport capability, can potentially offer excellent device characteristics and order-of-magnitude better energy-delay product over standard CMOS devices. Significant challenges in CNT synthesis prevent CNFETs today from achieving such ideal benefits. CNT density variation and metallic CNTs are the dominant type of CNT variations/imperfections that cause performance variation, large static power consumption, and yield degradation. We present an imperfection-aware design technique for CNFET digital VLSI circuits by: 1) Analytical models that are developed to analyze and quantify the effects of CNT density variation on device characteristics, gate and system levels delays. The analytical models, which were validated by comparison to real experimental/simulation data, enables us to examine the space of CNFET combinational, sequential and memory cells circuits to minimize delay variations. Using these model, we drive CNFET processing and circuit design guidelines to manage/overcome CNT density variation. 2) Analytical models that are developed to analyze the effects of metallic CNTs on device characteristics, gate and system levels delay and power consumption. Using our presented analytical models, which are again validated by comparison with simulation data, it is shown that the static power dissipation is a more critical issue than the delay and the dynamic power of CNFET circuits in the presence of m-CNTs. 3) CNT density variation and metallic CNTs can result in functional failure of CNFET circuits. The complete and compact model for CNFET probability of failure that consider CNT density variation and m-CNTs is presented. This analytical model is applied to analyze the logical functional failures. The presented model is extended to predict opportunities and limitations of CNFET technology at todays Gigascale integration and beyond.'</p>

Degree

thesis:*
Name thesis:degree_name
Computer Engineering
Level thesis:degree_level
Dissertation
Discipline thesis:degree_discipline
Electrical and Computer Engineering
Year dc:date.available
2014

Author and committee

dc:creator, dc:contributor.*
Author dc:creator
  • Arabi Mazraehshahi, Abbasali
Contributors dc:contributor
  • ZARKESH-HA, PAYMAN
  • Hossein-Zadeh, Mani
  • Leseman, Zayd
  • Plusquellic, James

Subjects

dc:subject × 8

Rights

Language dc:language
English

Identifiers

dc:identifier.*
Repository record dc:identifier
https://digitalrepository.unm.edu/ece_etds/16
OAI identifier oai:identifier
oai:digitalrepository.unm.edu:ece_etds-1015

Chain of custody

source
Harvested from
University of New Mexico
Base URL
digitalrepository.unm.edu/do/oai/
Last updated
2026-07-24
Source record
OAI-PMH GetRecord
citation

Arabi Mazraehshahi, Abbasali. Imperfection-Aware Design of CNFET Digital VLSI Circuits. Dissertation thesis, 2014. https://digitalrepository.unm.edu/ece_etds/16