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University of New Mexico

Energy consumption in networks on chip : efficiency and scaling

Abstract

dc:description.abstract

Computer architecture design is in a new era where performance is increased by replicating processing cores on a chip rather than making CPUs larger and faster. This design strategy is motivated by the superior energy efficiency of the multi-core architecture compared to the traditional monolithic CPU. If the trend continues as expected, the number of cores on a chip is predicted to grow exponentially over time as the density of transistors on a die increases. A major challenge to the efficiency of multi-core chips is the energy used for communication among cores over a Network on Chip (NoC). As the number of cores increases, this energy also increases, imposing serious constraints on design and performance of both applications and architectures. Therefore, understanding the impact of different design choices on NoC power and energy consumption is crucial to the success of the multi- and many-core designs. This dissertation proposes methods for modeling and optimizing energy consumption in multi- and many-core chips, with special focus on the energy used for communication on the NoC. We present a number of tools and models to optimize energy consumption and model its scaling behavior as the number of cores increases. We use synthetic traffic patterns and full system simulations to test and validate our methods. Finally, we take a step back and look at the evolution of computer hardware in the last 40 years and, using a scaling theory from biology, present a predictive theory for power-performance scaling in microprocessor systems.

Degree

thesis:*
Name thesis:degree_name
Computer Science
Level thesis:degree_level
Dissertation
Discipline thesis:degree_discipline
Department of Computer Science
Year
2012

Author and committee

dc:creator, dc:contributor.*
Author dc:creator
  • Bezerra, George
Contributors dc:contributor
  • Forrest, Stephanie
  • Moses, Melanie
  • Arnold, Dorian
  • Zarkesh-Ha, Payman

Subjects

dc:subject × 5

Rights

Language dc:language
English

Identifiers

dc:identifier.*
OAI identifier oai:identifier
oai:digitalrepository.unm.edu:cs_etds-1020

Chain of custody

source
Harvested from
University of New Mexico
Base URL
digitalrepository.unm.edu/do/oai/
Last updated
2026-07-24
Source record
OAI-PMH GetRecord
citation

Bezerra, George. Energy consumption in networks on chip : efficiency and scaling. Dissertation thesis, 2012. http://hdl.handle.net/1928/21020