Technological Solution beyond MOSFET and Binary Logic Device

Today’s technology is based on the binary number system-based circuitry, which is the outcome of the simple on and off switching mechanism of the prevailing transistors. Consideration of higher radix number system can eradicate or lessen many limitations of binary number system such as the saturation of Moore’s law. The most substantial potential benefits of higher radix approaches are the decrease of wiring complexity. Excessive scaling of the technologies has led the researchers beyond Binary Logic and MOSFET technology. TFET considered as one of the most promising options for low-power application for beyond MOSFET technologies. Graphene Nano Ribbon, due to its high-carrier mobility, tunable bandgap and its outstanding electrostatic control of device gate becomes ideal choice for channel material of TFET. This paper proposes double gated ultra-thin body (UTB) TFET device model using Graphene nano ribbon as the channel material. In this paper evaluation of the model by performing the comparative analysis with InAs as the channel material in terms of Ec-Ev on and off state and Id-Vg characteristics is presented. The feasibility of multi valued logic system in real-world rests on two serious aspects, such as, the easiness of mathematical approach for implementing the multivalued logic into today’s technology and the sufficiency of synthesis techniques. In this paper, we have focused on the different technology available for implementing multivalued logic especially ternary logic. Ternary logic devices are expected to lead to an exponential increase of the information handling capability, which binary logic cannot support. Memory capacitor or memcapacitor is an emerging device that exhibits hysteresis behavior, which can be manipulated by external parameters, such as, the applied electric field or voltage. One of the unique properties of the memcapacitor is that by using the percolation approach, we can achieve Metal-Insulator-Transition (MIT) phenomenon, which can be utilized to obtain a staggered hysteresis loop. For multivalued logic devices staggered hysteresis behavior is the critical requirement. In this paper, we propose a new conceptual design of a ternary logic device by vertically stacking dielectric material interleaved with layers of graphene nanoribbon (GNR) between two external metal plates. The proposed device structure displays the memcapacitive behavior with the fast switching metal-to-insulator transition in picosecond scale. The device model is later extended into a vertical-cascaded version, which acts as a ternary device.

Name thesis:degree_name

M.S.

Level thesis:degree_level

Masters

Discipline thesis:degree_discipline

Electrical Engineering (UMKC)

Grantor dc:publisher

University of Missouri -- Kansas City

Year dc:date.issued

2018

Author dc:creator

• Patel, Jill Arvindbhai

Advisor dc:contributor.advisor

• Chowdhury, Masud H.

Language dc:language.iso

en_US

Handle dc:identifier.uri

https://hdl.handle.net/10355/67039

OAI identifier oai:identifier

oai:mospace.umsystem.edu:10355/67039