Energy and Data Conversion Circuits for Low Power Sensory Systems

This dissertation focuses on the problem of increasing the lifetime of wireless sensors. This problem is addressed from two different angles: energy harvesting and data compression. Energy harvesting enables a sensor to extract energy from its environment and use it to power itself or recharge its batteries. Data compression, on the other hand, allows a sensor to save energy by reducing the radio transmission bandwidth. This dissertation proposes a fractal-based photodiode fabricated on standard CMOS process as an energy harvesting device with increased efficiency. Experiments show that, the fractal based photodiodes are 6% more efficient compared to the conventional square shaped photodiode. The fractal shape photodiode has more perimeter-to-area ratio which increases the lateral response, improving its efficiency. With increased efficiency, more current is generated but the open-circuit voltage still remains low (0:3V - 0:45V depending on illumination condition). These voltages have to be boosted up to higher values if they are going to be used to power up any sensory circuit or recharge a battery. We propose a switched-inductor DC-DC converter to boost the low voltage of the photodiodes to higher voltages. The proposed circuit uses two onchip switches and two off-chip components: an inductor and a capacitor. Experiments show a voltage up to 2:81V can be generated from a single photodiode of 1mm2 area. The voltage booster circuit achieved a conversion efficiency of 59%. Data compression was also explored in an effort to reduce energy consumption during radio transmission. An analog-to-digital converter (ADC), which can jointly perform the tasks of digital conversion and entropy encoding, has also been proposed in this dissertation. The joint data conversion/compression help savings in area and power resources, making it suitable for on-sensor compression. The proposed converter combines a cyclic converter architecture and Golomb-Rice entropy encoder. The converter hardware design is based on current-mode circuits and it was fabricated on a 0:5 m CMOS process and tested. Experiment results show a lossless compression ratio of 1:52 and a near-lossless compression of 5:2 can be achieved for 32 32 pixel image

Name thesis:degree_name

Ph. D.

Level thesis:degree_level

Doctoral

Discipline thesis:degree_discipline

Electrical and Computer Engineering (UMKC)

Grantor

University of Missouri--Kansas City

Year dc:date.issued

2013

Author dc:creator

• Ghosh, Suvradip

Advisor dc:contributor.advisor

• León-Salas, Walter D. (Walter Daniel)

Handle dc:identifier.uri

http://hdl.handle.net/10355/41509

OAI identifier oai:identifier

oai:mospace.umsystem.edu:10355/41509