Design of a low-power analog circuit for an implantable RFID-enabled device with passive pressure sensor
A low-power analog core for an implantable RFID-enabled pressure measurement system is designed. The analog core includes the power generation block for the system, the clock extractor for the digital core and the pressure sensor data converter. Circuit design constraints of low-power consumption and small form factor were followed in the implementation of the analog core. A new low-power analog-to-digital converter (ADC) for the pressure sensor is designed. The designed data converter is implemented using charge-distribution technique which consumes 90 µW of power and has a resolution of 12 bits making it suitable for such energy-constrained applications. The designed ADC is targeted towards a commercially available passive capacitive pressure sensor (microFab E1.3N). Cadence Virtuoso 6.1 Analog Design Environment simulators are used to design, test and compare the schematic and post-layout simulations of the components. The developed analog circuit will be a part of an implantable RFID chip with passive sensors which can communicate with RFID readers.
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