{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/99273"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/99273","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"Dependable design for low-cost ultra-low-power processors","abstract":"The student, Henry Duwe III, accepted the attached license on 2017-08-14 at 19:38.","abstract_html":"The student, Henry Duwe III, accepted the attached license on 2017-08-14 at 19:38.","abstract_has_math":false,"creators":["Duwe III, Henry John"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"Ph.D.","degree_level":"Dissertation","degree_discipline":"Electrical & Computer Engr","degree_department":null,"school":null,"contributors":["Kumar, Rakesh","Chen, Deming","Dolecek, Lara","Kim, Nam Sung"],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2018,"date_issued":"2018-03-13T15:44:34Z","date_published":"2018-03-13T15:44:34Z","updated_at":"2026-07-22T22:24:37Z","subjects":["Computer architecture","Low-power","Reliability","Security","Symbolic simulation","Co-analysis"],"languages":["en"],"rights":["Copyright 2017 Henry Duwe III"],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"http://hdl.handle.net/2142/99273","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Kumar, Rakesh","Chen, Deming","Dolecek, Lara","Kim, Nam Sung"]},{"key":"dc:creator","label":"Author","values":["Duwe III, Henry John"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2018-03-13T15:44:34Z","2017-08-15","2017-12"]},{"key":"dc:type","label":"Dc Type","values":["text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical & Computer Engr"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Dissertation"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Ph.D."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Computer architecture","Low-power","Reliability","Security","Symbolic simulation","Co-analysis"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["en"]},{"key":"dc:rights","label":"Dc Rights","values":["Copyright 2017 Henry Duwe III"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["http://hdl.handle.net/2142/99273"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["The student, Henry Duwe III, accepted the attached license on 2017-08-14 at 19:38.","The student, Henry Duwe III, submitted this Dissertation for approval on 2017-08-14 at 19:44.","This Dissertation was approved for publication on 2017-08-15 at 15:33.","DSpace SAF Submission Ingestion Package generated from Vireo submission #11602 on 2018-03-13 at 10:02:10","Emerging applications in the Internet of Things (IoT) domain, such as wearables, implantables, smart tags, and wireless sensor networks put severe power, cost, reliability, and security constraints on hardware system design. This dissertation focuses on the architecture and design of dependable ultra-low power computing systems. Specifically, it proposes architecture and design techniques that exploit the unique application and usage characteristics of future computing systems to deliver low power, while meeting the reliability and security constraints of these systems. First, this dissertation considers the challenge of achieving both low power and high reliability in SRAM memories. It proposes both an architectural technique to reduce the overheads of error correction and a technique that uses the nature of error correcting codes to allow lower voltage operation without sacrificing reliability. Next, this dissertation considers low power and low cost. By leveraging the fact that many IoT systems are embedded in nature and will run the same application for their entire lifetime, fine-grained usage characteristics of the hardware-software system can be determined at design time. This dissertation presents a novel hardware-software co-analysis based on symbolic simulation that can determine the possible states of the processor throughout any execution of a specific application. This enables power-gating where more gates are turned off for longer, bespoke processors customized to specific applications, and stricter determination of peak power bounds. Finally, this dissertation considers achieving secure IoT systems at low cost and power overhead. By leveraging the hardware-software co-analysis, this dissertation shows that gate-level information flow security guarantees can be provided without hardware overheads.","Submission original under an indefinite embargo labeled 'Open Access'. The submission was exported from vireo on 2018-03-13 without embargo terms","Made available in DSpace on 2018-03-13T15:44:34Z (GMT). No. of bitstreams: 3 DUWEIII-DISSERTATION-2017.pdf: 8645728 bytes, checksum: 09832f38cc2052debb1d505ba46b301a (MD5) LICENSE.txt: 4207 bytes, checksum: 6e17608d8143fcaeaa8443717c24a8b0 (MD5) PROQUEST_LICENSE.txt: 4553 bytes, checksum: 61a0710ca6ab33c3bd4dea16171c308e (MD5) Previous issue date: 2017-08-15"]},{"key":"dc:format","label":"Dc Format","values":["application/pdf"]},{"key":"dc:title","label":"Title","values":["Dependable design for low-cost ultra-low-power processors"]}]}],"canonical_facts":{"dc:contributor":["Kumar, Rakesh","Chen, Deming","Dolecek, Lara","Kim, Nam Sung"],"dc:creator":["Duwe III, Henry John"],"dc:date":["2018-03-13T15:44:34Z","2017-08-15","2017-12"],"dc:description":["The student, Henry Duwe III, accepted the attached license on 2017-08-14 at 19:38.","The student, Henry Duwe III, submitted this Dissertation for approval on 2017-08-14 at 19:44.","This Dissertation was approved for publication on 2017-08-15 at 15:33.","DSpace SAF Submission Ingestion Package generated from Vireo submission #11602 on 2018-03-13 at 10:02:10","Emerging applications in the Internet of Things (IoT) domain, such as wearables, implantables, smart tags, and wireless sensor networks put severe power, cost, reliability, and security constraints on hardware system design. This dissertation focuses on the architecture and design of dependable ultra-low power computing systems. Specifically, it proposes architecture and design techniques that exploit the unique application and usage characteristics of future computing systems to deliver low power, while meeting the reliability and security constraints of these systems. First, this dissertation considers the challenge of achieving both low power and high reliability in SRAM memories. It proposes both an architectural technique to reduce the overheads of error correction and a technique that uses the nature of error correcting codes to allow lower voltage operation without sacrificing reliability. Next, this dissertation considers low power and low cost. By leveraging the fact that many IoT systems are embedded in nature and will run the same application for their entire lifetime, fine-grained usage characteristics of the hardware-software system can be determined at design time. This dissertation presents a novel hardware-software co-analysis based on symbolic simulation that can determine the possible states of the processor throughout any execution of a specific application. This enables power-gating where more gates are turned off for longer, bespoke processors customized to specific applications, and stricter determination of peak power bounds. Finally, this dissertation considers achieving secure IoT systems at low cost and power overhead. By leveraging the hardware-software co-analysis, this dissertation shows that gate-level information flow security guarantees can be provided without hardware overheads.","Submission original under an indefinite embargo labeled 'Open Access'. The submission was exported from vireo on 2018-03-13 without embargo terms","Made available in DSpace on 2018-03-13T15:44:34Z (GMT). No. of bitstreams: 3 DUWEIII-DISSERTATION-2017.pdf: 8645728 bytes, checksum: 09832f38cc2052debb1d505ba46b301a (MD5) LICENSE.txt: 4207 bytes, checksum: 6e17608d8143fcaeaa8443717c24a8b0 (MD5) PROQUEST_LICENSE.txt: 4553 bytes, checksum: 61a0710ca6ab33c3bd4dea16171c308e (MD5) Previous issue date: 2017-08-15"],"dc:format":["application/pdf"],"dc:identifier":["http://hdl.handle.net/2142/99273"],"dc:language":["en"],"dc:rights":["Copyright 2017 Henry Duwe III"],"dc:subject":["Computer architecture","Low-power","Reliability","Security","Symbolic simulation","Co-analysis"],"dc:title":["Dependable design for low-cost ultra-low-power processors"],"dc:type":["text"],"thesis:degree_discipline":["Electrical & Computer Engr"],"thesis:degree_level":["Dissertation"],"thesis:degree_name":["Ph.D."],"thesis:institution_name":["University of Illinois at Urbana-Champaign"]},"updated_at":"2026-07-22T22:24:37Z"}