{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/98317"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/98317","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"Detection, diagnosis and modeling of ESD-induced soft failures - a gate-level and mixed-signal approach","abstract":"Electronic systems are an indispensable part of people's lives today. However, the reliability of electronic systems can be threatened by external stimuli such as Electrostatic Discharges (ESDs). ESDs can either physically damage an electronic system or let it malfunction without damaging it. Therefore, a lot of design work and qualification testings are needed by manufacturers to improve the robustness against the negative effects of ESDs. The trial-and-error based solution implementation has incurred huge costs to companies in terms of labor and time. Despite the ever-increasing effort being devoted to solving ESD-related problems, cases of field returns still happen, and a significant portion can be attributed to soft failure induced by system-level ESD. Despite that, the ESD-induced permanent failures are well-studied and protection mechanisms have proven to work, the studies on ESD-induced soft failures are all on the physical and transistor level. In this thesis, we studied ESD-induced soft failures by first conducting case studies of injecting ESDs into physical devices and observing the application level symptoms of the failures, and then performing simulation-based ESD injections on a well-known instruction-set-architecture. For the first time, we correlated the physical level ESD event to high-level system behavior. We implemented a mixed-signal-simulation-based fault injection environment and device models to allow ESDs to be injected to target systems. By injecting different types of ESDs into the target system, we, for the first time, identified gate-level bit-flip patterns from a SPICE level high-voltage event. Our experimental results show that the extent of register value corruption can be single-bit or widespread, and the bit flips manifested can affect the system in multiple ways. We also demonstrated low-cost protection measures for some of the failures resulted.","abstract_html":"Electronic systems are an indispensable part of people's lives today. However, the reliability of electronic systems can be threatened by external stimuli such as Electrostatic Discharges (ESDs). ESDs can either physically damage an electronic system or let it malfunction without damaging it. Therefore, a lot of design work and qualification testings are needed by manufacturers to improve the robustness against the negative effects of ESDs. The trial-and-error based solution implementation has incurred huge costs to companies in terms of labor and time. Despite the ever-increasing effort being devoted to solving ESD-related problems, cases of field returns still happen, and a significant portion can be attributed to soft failure induced by system-level ESD. Despite that, the ESD-induced permanent failures are well-studied and protection mechanisms have proven to work, the studies on ESD-induced soft failures are all on the physical and transistor level. In this thesis, we studied ESD-induced soft failures by first conducting case studies of injecting ESDs into physical devices and observing the application level symptoms of the failures, and then performing simulation-based ESD injections on a well-known instruction-set-architecture. For the first time, we correlated the physical level ESD event to high-level system behavior. We implemented a mixed-signal-simulation-based fault injection environment and device models to allow ESDs to be injected to target systems. By injecting different types of ESDs into the target system, we, for the first time, identified gate-level bit-flip patterns from a SPICE level high-voltage event. Our experimental results show that the extent of register value corruption can be single-bit or widespread, and the bit flips manifested can affect the system in multiple ways. We also demonstrated low-cost protection measures for some of the failures resulted.","abstract_has_math":false,"creators":["Jiang, Rui"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"M.S.","degree_level":"Thesis","degree_discipline":"Electrical & Computer Engr","degree_department":null,"school":null,"contributors":["Vasudevan, Shobha"],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2017,"date_issued":"2017-09-29T17:52:35Z","date_published":"2017-09-29T17:52:35Z","updated_at":"2026-07-22T22:24:35Z","subjects":["Electrostatic discharges (ESD)","Reliability","Fault modeling","Mixed-signal simulation","Fault injection","Fault detection"],"languages":["en"],"rights":["Copyright 2017 Rui Jiang"],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"http://hdl.handle.net/2142/98317","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Vasudevan, Shobha"]},{"key":"dc:creator","label":"Author","values":["Jiang, Rui"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2017-09-29T17:52:35Z","2019-09-30T09:15:32Z","2017-07-21","2017-08"]},{"key":"dc:type","label":"Dc Type","values":["text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical & Computer Engr"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Thesis"]},{"key":"thesis:degree_name","label":"Degree Name","values":["M.S."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Electrostatic discharges (ESD)","Reliability","Fault modeling","Mixed-signal simulation","Fault injection","Fault detection"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["en"]},{"key":"dc:rights","label":"Dc Rights","values":["Copyright 2017 Rui Jiang"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["http://hdl.handle.net/2142/98317"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["Electronic systems are an indispensable part of people's lives today. However, the reliability of electronic systems can be threatened by external stimuli such as Electrostatic Discharges (ESDs). ESDs can either physically damage an electronic system or let it malfunction without damaging it. Therefore, a lot of design work and qualification testings are needed by manufacturers to improve the robustness against the negative effects of ESDs. The trial-and-error based solution implementation has incurred huge costs to companies in terms of labor and time. Despite the ever-increasing effort being devoted to solving ESD-related problems, cases of field returns still happen, and a significant portion can be attributed to soft failure induced by system-level ESD. Despite that, the ESD-induced permanent failures are well-studied and protection mechanisms have proven to work, the studies on ESD-induced soft failures are all on the physical and transistor level. In this thesis, we studied ESD-induced soft failures by first conducting case studies of injecting ESDs into physical devices and observing the application level symptoms of the failures, and then performing simulation-based ESD injections on a well-known instruction-set-architecture. For the first time, we correlated the physical level ESD event to high-level system behavior. We implemented a mixed-signal-simulation-based fault injection environment and device models to allow ESDs to be injected to target systems. By injecting different types of ESDs into the target system, we, for the first time, identified gate-level bit-flip patterns from a SPICE level high-voltage event. Our experimental results show that the extent of register value corruption can be single-bit or widespread, and the bit flips manifested can affect the system in multiple ways. We also demonstrated low-cost protection measures for some of the failures resulted.","Submission published under a 24 month embargo labeled 'Closed Access', the embargo will last until 2019-08-01","The student, Rui Jiang, accepted the attached license on 2017-07-21 at 12:32.","The student, Rui Jiang, submitted this Thesis for approval on 2017-07-21 at 12:42.","This Thesis was approved for publication on 2017-07-21 at 13:02.","DSpace SAF Submission Ingestion Package generated from Vireo submission #11577 on 2017-09-29 at 11:20:17","Made available in DSpace on 2017-09-29T17:52:35Z (GMT). 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However, the reliability of electronic systems can be threatened by external stimuli such as Electrostatic Discharges (ESDs). ESDs can either physically damage an electronic system or let it malfunction without damaging it. Therefore, a lot of design work and qualification testings are needed by manufacturers to improve the robustness against the negative effects of ESDs. The trial-and-error based solution implementation has incurred huge costs to companies in terms of labor and time. Despite the ever-increasing effort being devoted to solving ESD-related problems, cases of field returns still happen, and a significant portion can be attributed to soft failure induced by system-level ESD. Despite that, the ESD-induced permanent failures are well-studied and protection mechanisms have proven to work, the studies on ESD-induced soft failures are all on the physical and transistor level. In this thesis, we studied ESD-induced soft failures by first conducting case studies of injecting ESDs into physical devices and observing the application level symptoms of the failures, and then performing simulation-based ESD injections on a well-known instruction-set-architecture. For the first time, we correlated the physical level ESD event to high-level system behavior. We implemented a mixed-signal-simulation-based fault injection environment and device models to allow ESDs to be injected to target systems. By injecting different types of ESDs into the target system, we, for the first time, identified gate-level bit-flip patterns from a SPICE level high-voltage event. Our experimental results show that the extent of register value corruption can be single-bit or widespread, and the bit flips manifested can affect the system in multiple ways. We also demonstrated low-cost protection measures for some of the failures resulted.","Submission published under a 24 month embargo labeled 'Closed Access', the embargo will last until 2019-08-01","The student, Rui Jiang, accepted the attached license on 2017-07-21 at 12:32.","The student, Rui Jiang, submitted this Thesis for approval on 2017-07-21 at 12:42.","This Thesis was approved for publication on 2017-07-21 at 13:02.","DSpace SAF Submission Ingestion Package generated from Vireo submission #11577 on 2017-09-29 at 11:20:17","Made available in DSpace on 2017-09-29T17:52:35Z (GMT). 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