{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/98312"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/98312","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"Acceleration of real-time face recognition pipeline on heterogeneous hardware platforms","abstract":"In recent years, advancements in machine learning techniques, and specifically, deep learning methods, have started to create a great impact in the world. With the advent of deep neural network, we are able to achieve unprecedented results in previously unsolvable computer vision tasks. Face recognition, one of the critical computer vision tasks, also sees breakthrough in terms of accuracy. This thesis presents an accelerated and optimized end-to-end face recognition pipeline. Such a pipeline consists of three stages: face detection, alignment, and face recognition/verification. Algorithms for these jobs are extremely computation intensive and thus real-time application was not attainable. In order to bring about the goal of high definition real-time multi-face recognition, we leverage different types of hardware to accelerate detection and recognition stages, which are the most time-consuming stages of the recognition pipeline. To achieve this goal, we leverage an embedded Graphic Processing Unit (GPU) platform as the front end, to perform video capture and face detection. For the back end, we employ a powerful Field-Programming Gate Arrays (FPGA) equipped server, which runs a state-of-the-art deep neural network to recognize faces streamed from the front end with low latency. With the two acceleration schemes targeting GPUs and FPGAs, respectively, we are able to achieve real-time performance for the overall task, and such face recognition system can be widely adopted for various applications.","abstract_html":"In recent years, advancements in machine learning techniques, and specifically, deep learning methods, have started to create a great impact in the world. With the advent of deep neural network, we are able to achieve unprecedented results in previously unsolvable computer vision tasks. Face recognition, one of the critical computer vision tasks, also sees breakthrough in terms of accuracy. This thesis presents an accelerated and optimized end-to-end face recognition pipeline. Such a pipeline consists of three stages: face detection, alignment, and face recognition/verification. Algorithms for these jobs are extremely computation intensive and thus real-time application was not attainable. In order to bring about the goal of high definition real-time multi-face recognition, we leverage different types of hardware to accelerate detection and recognition stages, which are the most time-consuming stages of the recognition pipeline. To achieve this goal, we leverage an embedded Graphic Processing Unit (GPU) platform as the front end, to perform video capture and face detection. For the back end, we employ a powerful Field-Programming Gate Arrays (FPGA) equipped server, which runs a state-of-the-art deep neural network to recognize faces streamed from the front end with low latency. With the two acceleration schemes targeting GPUs and FPGAs, respectively, we are able to achieve real-time performance for the overall task, and such face recognition system can be widely adopted for various applications.","abstract_has_math":false,"creators":["Zhuge, Chuanhao"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"M.S.","degree_level":"Thesis","degree_discipline":"Electrical & Computer Engr","degree_department":null,"school":null,"contributors":["Chen, Deming"],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2017,"date_issued":"2017-09-29T17:52:33Z","date_published":"2017-09-29T17:52:33Z","updated_at":"2026-07-22T22:24:35Z","subjects":["Convolutional neural network","Deep neural network","Fast Fourier-transform","Winograd","High-level synthesis","Field-programming gate arrays (FPGA)"],"languages":["en"],"rights":["Copyright 2017 Chuanhao Zhuge"],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"http://hdl.handle.net/2142/98312","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Chen, Deming"]},{"key":"dc:creator","label":"Author","values":["Zhuge, Chuanhao"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2017-09-29T17:52:33Z","2019-09-30T09:15:20Z","2017-07-21","2017-08"]},{"key":"dc:type","label":"Dc Type","values":["text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical & Computer Engr"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Thesis"]},{"key":"thesis:degree_name","label":"Degree Name","values":["M.S."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Convolutional neural network","Deep neural network","Fast Fourier-transform","Winograd","High-level synthesis","Field-programming gate arrays (FPGA)"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["en"]},{"key":"dc:rights","label":"Dc Rights","values":["Copyright 2017 Chuanhao Zhuge"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["http://hdl.handle.net/2142/98312"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["In recent years, advancements in machine learning techniques, and specifically, deep learning methods, have started to create a great impact in the world. With the advent of deep neural network, we are able to achieve unprecedented results in previously unsolvable computer vision tasks. Face recognition, one of the critical computer vision tasks, also sees breakthrough in terms of accuracy. This thesis presents an accelerated and optimized end-to-end face recognition pipeline. Such a pipeline consists of three stages: face detection, alignment, and face recognition/verification. Algorithms for these jobs are extremely computation intensive and thus real-time application was not attainable. In order to bring about the goal of high definition real-time multi-face recognition, we leverage different types of hardware to accelerate detection and recognition stages, which are the most time-consuming stages of the recognition pipeline. To achieve this goal, we leverage an embedded Graphic Processing Unit (GPU) platform as the front end, to perform video capture and face detection. For the back end, we employ a powerful Field-Programming Gate Arrays (FPGA) equipped server, which runs a state-of-the-art deep neural network to recognize faces streamed from the front end with low latency. With the two acceleration schemes targeting GPUs and FPGAs, respectively, we are able to achieve real-time performance for the overall task, and such face recognition system can be widely adopted for various applications.","Submission published under a 24 month embargo labeled 'Closed Access', the embargo will last until 2019-08-01","The student, Chuanhao Zhuge, accepted the attached license on 2017-07-20 at 17:00.","The student, Chuanhao Zhuge, submitted this Thesis for approval on 2017-07-20 at 17:35.","This Thesis was approved for publication on 2017-07-21 at 08:29.","DSpace SAF Submission Ingestion Package generated from Vireo submission #11565 on 2017-09-29 at 11:20:07","Made available in DSpace on 2017-09-29T17:52:33Z (GMT). No. of bitstreams: 2 ZHUGE-THESIS-2017.pdf: 8815308 bytes, checksum: 314ee48cf90fd466f3511201aacf5d0d (MD5) LICENSE.txt: 4211 bytes, checksum: 9b901652b1adb582309613802a58dbdc (MD5) Previous issue date: 2017-07-21","Embargo set by: Colleen Fallaw for item 103520 Lift date: 2019-09-29T17:52:45Z Reason: Author requested closed access (OA after 2yrs) in Vireo ETD system","Limited Restriction Lifted for Item 103520 on 2019-09-30T09:15:20Z."]},{"key":"dc:format","label":"Dc Format","values":["application/pdf"]},{"key":"dc:title","label":"Title","values":["Acceleration of real-time face recognition pipeline on heterogeneous hardware platforms"]}]}],"canonical_facts":{"dc:contributor":["Chen, Deming"],"dc:creator":["Zhuge, Chuanhao"],"dc:date":["2017-09-29T17:52:33Z","2019-09-30T09:15:20Z","2017-07-21","2017-08"],"dc:description":["In recent years, advancements in machine learning techniques, and specifically, deep learning methods, have started to create a great impact in the world. With the advent of deep neural network, we are able to achieve unprecedented results in previously unsolvable computer vision tasks. Face recognition, one of the critical computer vision tasks, also sees breakthrough in terms of accuracy. This thesis presents an accelerated and optimized end-to-end face recognition pipeline. Such a pipeline consists of three stages: face detection, alignment, and face recognition/verification. Algorithms for these jobs are extremely computation intensive and thus real-time application was not attainable. In order to bring about the goal of high definition real-time multi-face recognition, we leverage different types of hardware to accelerate detection and recognition stages, which are the most time-consuming stages of the recognition pipeline. To achieve this goal, we leverage an embedded Graphic Processing Unit (GPU) platform as the front end, to perform video capture and face detection. For the back end, we employ a powerful Field-Programming Gate Arrays (FPGA) equipped server, which runs a state-of-the-art deep neural network to recognize faces streamed from the front end with low latency. With the two acceleration schemes targeting GPUs and FPGAs, respectively, we are able to achieve real-time performance for the overall task, and such face recognition system can be widely adopted for various applications.","Submission published under a 24 month embargo labeled 'Closed Access', the embargo will last until 2019-08-01","The student, Chuanhao Zhuge, accepted the attached license on 2017-07-20 at 17:00.","The student, Chuanhao Zhuge, submitted this Thesis for approval on 2017-07-20 at 17:35.","This Thesis was approved for publication on 2017-07-21 at 08:29.","DSpace SAF Submission Ingestion Package generated from Vireo submission #11565 on 2017-09-29 at 11:20:07","Made available in DSpace on 2017-09-29T17:52:33Z (GMT). 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