{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/97744"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/97744","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"Ring oscillator based injection locked clock multiplier","abstract":"This thesis describes a ring-based injection locked clock multiplier (ILCM) designed with the goal of generating a high-frequency and low-jitter clock. Building on prior research done on injection locking, this design uses a reference frequency doubling technique to push the noise bandwidth of the circuit to Fref/3 to suppress DCO noise to a large extent. A background duty cycle error correction technique is employed to correct errors on the doubled clock that could be detrimental to performance. The design also modifies an existing architecture to achieve type-II suppression of DCO noise in order to fully suppress the flicker noise which becomes prevalent in low process nodes. The prototype ILCM was fabricated in TSMC 65 nm CMOS technology. Thorough testing was performed to characterize the effectiveness of the aforementioned techniques. The circuit achieves 340 fsrms integrated jitter when operating at 5 GHz while only consuming 5.3 mW of power. The ILCM's figure of merit, -242.4 dB, is on par with state-of-the-art ring-based clock multipliers while operating at a much higher output frequency and multiplication factor than previously published work. These results indicate the effectiveness of reference frequency doubling in a ring-based, high-performance clock multiplier design.","abstract_html":"This thesis describes a ring-based injection locked clock multiplier (ILCM) designed with the goal of generating a high-frequency and low-jitter clock. Building on prior research done on injection locking, this design uses a reference frequency doubling technique to push the noise bandwidth of the circuit to Fref/3 to suppress DCO noise to a large extent. A background duty cycle error correction technique is employed to correct errors on the doubled clock that could be detrimental to performance. The design also modifies an existing architecture to achieve type-II suppression of DCO noise in order to fully suppress the flicker noise which becomes prevalent in low process nodes. The prototype ILCM was fabricated in TSMC 65 nm CMOS technology. Thorough testing was performed to characterize the effectiveness of the aforementioned techniques. The circuit achieves 340 fsrms integrated jitter when operating at 5 GHz while only consuming 5.3 mW of power. The ILCM's figure of merit, -242.4 dB, is on par with state-of-the-art ring-based clock multipliers while operating at a much higher output frequency and multiplication factor than previously published work. These results indicate the effectiveness of reference frequency doubling in a ring-based, high-performance clock multiplier design.","abstract_has_math":false,"creators":["Coombs, Daniel R"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"M.S.","degree_level":"Thesis","degree_discipline":"Electrical & Computer Engr","degree_department":null,"school":null,"contributors":["Hanumolu, Pavan K."],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2017,"date_issued":"2017-08-10T20:33:10Z","date_published":"2017-08-10T20:33:10Z","updated_at":"2026-07-22T22:24:34Z","subjects":["Phase-locked loop","Injection locking","Ring oscillator","High-performance clocking"],"languages":["en"],"rights":["Copyright 2017 Daniel Coombs"],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"http://hdl.handle.net/2142/97744","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Hanumolu, Pavan K."]},{"key":"dc:creator","label":"Author","values":["Coombs, Daniel R"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2017-08-10T20:33:10Z","2019-08-11T09:15:32Z","2017-04-24","2017-05"]},{"key":"dc:type","label":"Dc Type","values":["text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical & Computer Engr"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Thesis"]},{"key":"thesis:degree_name","label":"Degree Name","values":["M.S."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Phase-locked loop","Injection locking","Ring oscillator","High-performance clocking"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["en"]},{"key":"dc:rights","label":"Dc Rights","values":["Copyright 2017 Daniel Coombs"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["http://hdl.handle.net/2142/97744"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["This thesis describes a ring-based injection locked clock multiplier (ILCM) designed with the goal of generating a high-frequency and low-jitter clock. Building on prior research done on injection locking, this design uses a reference frequency doubling technique to push the noise bandwidth of the circuit to Fref/3 to suppress DCO noise to a large extent. A background duty cycle error correction technique is employed to correct errors on the doubled clock that could be detrimental to performance. The design also modifies an existing architecture to achieve type-II suppression of DCO noise in order to fully suppress the flicker noise which becomes prevalent in low process nodes. The prototype ILCM was fabricated in TSMC 65 nm CMOS technology. Thorough testing was performed to characterize the effectiveness of the aforementioned techniques. The circuit achieves 340 fsrms integrated jitter when operating at 5 GHz while only consuming 5.3 mW of power. The ILCM's figure of merit, -242.4 dB, is on par with state-of-the-art ring-based clock multipliers while operating at a much higher output frequency and multiplication factor than previously published work. These results indicate the effectiveness of reference frequency doubling in a ring-based, high-performance clock multiplier design.","Submission published under a 24 month embargo labeled 'U of I Access', the embargo will last until 2019-05-01","The student, Daniel Coombs, accepted the attached license on 2017-04-19 at 12:30.","The student, Daniel Coombs, submitted this Thesis for approval on 2017-04-19 at 12:40.","This Thesis was approved for publication on 2017-04-24 at 10:52.","DSpace SAF Submission Ingestion Package generated from Vireo submission #10900 on 2017-08-10 at 15:06:19","Made available in DSpace on 2017-08-10T20:33:10Z (GMT). No. of bitstreams: 2 COOMBS-THESIS-2017.pdf: 17117986 bytes, checksum: ec7fe0620eeacc03b10280f599707f12 (MD5) LICENSE.txt: 4210 bytes, checksum: 3feb9e22d7156ccc8e8a990434f3b166 (MD5) Previous issue date: 2017-04-24","Embargo set by: Colleen Fallaw for item 102797 Lift date: 2019-08-10T21:27:21Z Reason: Author requested U of Illinois access only (OA after 2yrs) in Vireo ETD system","U of I Only Restriction Lifted for Item 102797 on 2019-08-11T09:15:32Z."]},{"key":"dc:format","label":"Dc Format","values":["application/pdf"]},{"key":"dc:title","label":"Title","values":["Ring oscillator based injection locked clock multiplier"]}]}],"canonical_facts":{"dc:contributor":["Hanumolu, Pavan K."],"dc:creator":["Coombs, Daniel R"],"dc:date":["2017-08-10T20:33:10Z","2019-08-11T09:15:32Z","2017-04-24","2017-05"],"dc:description":["This thesis describes a ring-based injection locked clock multiplier (ILCM) designed with the goal of generating a high-frequency and low-jitter clock. Building on prior research done on injection locking, this design uses a reference frequency doubling technique to push the noise bandwidth of the circuit to Fref/3 to suppress DCO noise to a large extent. A background duty cycle error correction technique is employed to correct errors on the doubled clock that could be detrimental to performance. The design also modifies an existing architecture to achieve type-II suppression of DCO noise in order to fully suppress the flicker noise which becomes prevalent in low process nodes. The prototype ILCM was fabricated in TSMC 65 nm CMOS technology. Thorough testing was performed to characterize the effectiveness of the aforementioned techniques. The circuit achieves 340 fsrms integrated jitter when operating at 5 GHz while only consuming 5.3 mW of power. The ILCM's figure of merit, -242.4 dB, is on par with state-of-the-art ring-based clock multipliers while operating at a much higher output frequency and multiplication factor than previously published work. These results indicate the effectiveness of reference frequency doubling in a ring-based, high-performance clock multiplier design.","Submission published under a 24 month embargo labeled 'U of I Access', the embargo will last until 2019-05-01","The student, Daniel Coombs, accepted the attached license on 2017-04-19 at 12:30.","The student, Daniel Coombs, submitted this Thesis for approval on 2017-04-19 at 12:40.","This Thesis was approved for publication on 2017-04-24 at 10:52.","DSpace SAF Submission Ingestion Package generated from Vireo submission #10900 on 2017-08-10 at 15:06:19","Made available in DSpace on 2017-08-10T20:33:10Z (GMT). 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