{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/97663"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/97663","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"Transient circuit simulation of MOSFETs using latency insertion method","abstract":"This Thesis was approved for publication on 2017-03-20 at 11:44.","abstract_html":"This Thesis was approved for publication on 2017-03-20 at 11:44.","abstract_has_math":false,"creators":["Hajimiri, Maryam"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"M.S.","degree_level":"Thesis","degree_discipline":"Electrical & Computer Engr","degree_department":null,"school":null,"contributors":["Schutt-Ainé, José"],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2017,"date_issued":"2017-08-10T20:32:34Z","date_published":"2017-08-10T20:32:34Z","updated_at":"2026-07-22T22:24:34Z","subjects":["Latency insertion method (LIM)","Metal-oxide semiconductor field-effect transistors (MOSFET) model"],"languages":["en"],"rights":["Copyright 2017 Maryam Hajimiri"],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"http://hdl.handle.net/2142/97663","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Schutt-Ainé, José"]},{"key":"dc:creator","label":"Author","values":["Hajimiri, Maryam"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2017-08-10T20:32:34Z","2019-08-11T09:15:35Z","2017-03-20","2017-05"]},{"key":"dc:type","label":"Dc Type","values":["text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical & Computer Engr"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Thesis"]},{"key":"thesis:degree_name","label":"Degree Name","values":["M.S."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Latency insertion method (LIM)","Metal-oxide semiconductor field-effect transistors (MOSFET) model"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["en"]},{"key":"dc:rights","label":"Dc Rights","values":["Copyright 2017 Maryam Hajimiri"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["http://hdl.handle.net/2142/97663"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["This Thesis was approved for publication on 2017-03-20 at 11:44.","DSpace SAF Submission Ingestion Package generated from Vireo submission #10601 on 2017-08-10 at 15:04:39","Made available in DSpace on 2017-08-10T20:32:34Z (GMT). No. of bitstreams: 2 HAJIMIRI-THESIS-2017.pdf: 2732064 bytes, checksum: 90a6e72457a2e9a7c647f0f404916766 (MD5) LICENSE.txt: 4212 bytes, checksum: 6b90bf490ea18d1f39be84ea8cfeb71c (MD5) Previous issue date: 2017-03-20","Embargo set by: Colleen Fallaw for item 102716 Lift date: 2019-08-10T21:27:21Z Reason: Author requested U of Illinois access only (OA after 2yrs) in Vireo ETD system","U of I Only Restriction Lifted for Item 102716 on 2019-08-11T09:15:35Z.","With the remarkable success in the electronics industry, the designers working in the engineering community are constantly demanding computer-based analysis tools that provide faster yet more accurate simulation results. The design engineers are required to efficiently address the design issues at early stages by performing extensive circuit simulations, which may be time consuming if the number of possible design approaches is big and the simulation runtime for each is long. Hence the need for computer-aided design tools with higher speed and performance. This thesis presents an approach to utilize the latency insertion method (LIM) in the transient simulation of the circuits involving metal-oxide semiconductor field-effect transistors (MOSFETs) with the use of advanced transistor models. Simulations via LIM achieve higher computational speed, especially in nonlinear systems. A more accurate simulation of digital and analog circuits can be performed by taking into account the nonlinear charge storage capacitances and other second-order effects in short-channel devices. Hence, the SPICE LEVEL 3 transistor model for MOSFETs is employed in this work. Several computer simulations validate the method and indicate the high-level models provide better accuracy.","Submission published under a 24 month embargo labeled 'U of I Access', the embargo will last until 2019-05-01","The student, Maryam Hajimiri, accepted the attached license on 2017-03-17 at 16:09.","The student, Maryam Hajimiri, submitted this Thesis for approval on 2017-03-17 at 16:19."]},{"key":"dc:format","label":"Dc Format","values":["application/pdf"]},{"key":"dc:title","label":"Title","values":["Transient circuit simulation of MOSFETs using latency insertion method"]}]}],"canonical_facts":{"dc:contributor":["Schutt-Ainé, José"],"dc:creator":["Hajimiri, Maryam"],"dc:date":["2017-08-10T20:32:34Z","2019-08-11T09:15:35Z","2017-03-20","2017-05"],"dc:description":["This Thesis was approved for publication on 2017-03-20 at 11:44.","DSpace SAF Submission Ingestion Package generated from Vireo submission #10601 on 2017-08-10 at 15:04:39","Made available in DSpace on 2017-08-10T20:32:34Z (GMT). No. of bitstreams: 2 HAJIMIRI-THESIS-2017.pdf: 2732064 bytes, checksum: 90a6e72457a2e9a7c647f0f404916766 (MD5) LICENSE.txt: 4212 bytes, checksum: 6b90bf490ea18d1f39be84ea8cfeb71c (MD5) Previous issue date: 2017-03-20","Embargo set by: Colleen Fallaw for item 102716 Lift date: 2019-08-10T21:27:21Z Reason: Author requested U of Illinois access only (OA after 2yrs) in Vireo ETD system","U of I Only Restriction Lifted for Item 102716 on 2019-08-11T09:15:35Z.","With the remarkable success in the electronics industry, the designers working in the engineering community are constantly demanding computer-based analysis tools that provide faster yet more accurate simulation results. The design engineers are required to efficiently address the design issues at early stages by performing extensive circuit simulations, which may be time consuming if the number of possible design approaches is big and the simulation runtime for each is long. Hence the need for computer-aided design tools with higher speed and performance. This thesis presents an approach to utilize the latency insertion method (LIM) in the transient simulation of the circuits involving metal-oxide semiconductor field-effect transistors (MOSFETs) with the use of advanced transistor models. Simulations via LIM achieve higher computational speed, especially in nonlinear systems. A more accurate simulation of digital and analog circuits can be performed by taking into account the nonlinear charge storage capacitances and other second-order effects in short-channel devices. Hence, the SPICE LEVEL 3 transistor model for MOSFETs is employed in this work. Several computer simulations validate the method and indicate the high-level models provide better accuracy.","Submission published under a 24 month embargo labeled 'U of I Access', the embargo will last until 2019-05-01","The student, Maryam Hajimiri, accepted the attached license on 2017-03-17 at 16:09.","The student, Maryam Hajimiri, submitted this Thesis for approval on 2017-03-17 at 16:19."],"dc:format":["application/pdf"],"dc:identifier":["http://hdl.handle.net/2142/97663"],"dc:language":["en"],"dc:rights":["Copyright 2017 Maryam Hajimiri"],"dc:subject":["Latency insertion method (LIM)","Metal-oxide semiconductor field-effect transistors (MOSFET) model"],"dc:title":["Transient circuit simulation of MOSFETs using latency insertion method"],"dc:type":["text"],"thesis:degree_discipline":["Electrical & Computer Engr"],"thesis:degree_level":["Thesis"],"thesis:degree_name":["M.S."],"thesis:institution_name":["University of Illinois at Urbana-Champaign"]},"updated_at":"2026-07-22T22:24:34Z"}