{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/97551"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/97551","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"Synthesis constraint optimization for near-threshold voltage design","abstract":"Near-threshold voltage (NTV) design is a viable solution to many embedded systems which require high energy efficiencies and low performances, but it makes them vulnerable to process variation. Increasing the size of devices and/or decreasing the operating frequencies of the systems can be the solutions, but these methods decrease the energy efficiencies which is cancelling out the benefit from NTV. In this work, we test multiple logic synthesis options on openMSP430 microcontroller with TSMC 65nm technology library and suggest the optimal design points to the future IC designers. We find synthesizing the microcontroller with the minimum design constraint gives us the best performance and energy consumption. We also run Monte Carlo simulation to show the estimated yield rate of the suggested design points.","abstract_html":"Near-threshold voltage (NTV) design is a viable solution to many embedded systems which require high energy efficiencies and low performances, but it makes them vulnerable to process variation. Increasing the size of devices and/or decreasing the operating frequencies of the systems can be the solutions, but these methods decrease the energy efficiencies which is cancelling out the benefit from NTV. In this work, we test multiple logic synthesis options on openMSP430 microcontroller with TSMC 65nm technology library and suggest the optimal design points to the future IC designers. We find synthesizing the microcontroller with the minimum design constraint gives us the best performance and energy consumption. We also run Monte Carlo simulation to show the estimated yield rate of the suggested design points.","abstract_has_math":false,"creators":["Min, David"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"M.S.","degree_level":"Thesis","degree_discipline":"Electrical & Computer Engr","degree_department":null,"school":null,"contributors":["Kim, Nam Sung"],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2017,"date_issued":"2017-08-10T19:51:47Z","date_published":"2017-08-10T19:51:47Z","updated_at":"2026-07-22T22:24:34Z","subjects":["Near-threshold voltage","Low-energy","Embedded systems"],"languages":["en"],"rights":["Copyright 2017 David Min"],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"http://hdl.handle.net/2142/97551","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Kim, Nam Sung"]},{"key":"dc:creator","label":"Author","values":["Min, David"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2017-08-10T19:51:47Z","2019-08-11T09:15:31Z","2017-04-17","2017-05"]},{"key":"dc:type","label":"Dc Type","values":["text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical & Computer Engr"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Thesis"]},{"key":"thesis:degree_name","label":"Degree Name","values":["M.S."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Near-threshold voltage","Low-energy","Embedded systems"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["en"]},{"key":"dc:rights","label":"Dc Rights","values":["Copyright 2017 David Min"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["http://hdl.handle.net/2142/97551"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["Near-threshold voltage (NTV) design is a viable solution to many embedded systems which require high energy efficiencies and low performances, but it makes them vulnerable to process variation. Increasing the size of devices and/or decreasing the operating frequencies of the systems can be the solutions, but these methods decrease the energy efficiencies which is cancelling out the benefit from NTV. In this work, we test multiple logic synthesis options on openMSP430 microcontroller with TSMC 65nm technology library and suggest the optimal design points to the future IC designers. We find synthesizing the microcontroller with the minimum design constraint gives us the best performance and energy consumption. We also run Monte Carlo simulation to show the estimated yield rate of the suggested design points.","Submission published under a 24 month embargo labeled 'Closed Access', the embargo will last until 2019-05-01","The student, David Min, accepted the attached license on 2017-04-10 at 11:14.","The student, David Min, submitted this Thesis for approval on 2017-04-10 at 11:15.","This Thesis was approved for publication on 2017-04-17 at 13:26.","DSpace SAF Submission Ingestion Package generated from Vireo submission #10674 on 2017-08-10 at 14:30:17","Made available in DSpace on 2017-08-10T19:51:47Z (GMT). No. of bitstreams: 2 MIN-THESIS-2017.pdf: 745962 bytes, checksum: f2241c812d253c507ad9549bcab092f7 (MD5) LICENSE.txt: 4206 bytes, checksum: d1aea14a8aba5c04ad18d6448eef95fe (MD5) Previous issue date: 2017-04-17","Embargo set by: Colleen Fallaw for item 102604 Lift date: 2019-08-10T21:25:30Z Reason: Author requested closed access (OA after 2yrs) in Vireo ETD system","Limited Restriction Lifted for Item 102604 on 2019-08-11T09:15:31Z."]},{"key":"dc:format","label":"Dc Format","values":["application/pdf"]},{"key":"dc:title","label":"Title","values":["Synthesis constraint optimization for near-threshold voltage design"]}]}],"canonical_facts":{"dc:contributor":["Kim, Nam Sung"],"dc:creator":["Min, David"],"dc:date":["2017-08-10T19:51:47Z","2019-08-11T09:15:31Z","2017-04-17","2017-05"],"dc:description":["Near-threshold voltage (NTV) design is a viable solution to many embedded systems which require high energy efficiencies and low performances, but it makes them vulnerable to process variation. Increasing the size of devices and/or decreasing the operating frequencies of the systems can be the solutions, but these methods decrease the energy efficiencies which is cancelling out the benefit from NTV. In this work, we test multiple logic synthesis options on openMSP430 microcontroller with TSMC 65nm technology library and suggest the optimal design points to the future IC designers. We find synthesizing the microcontroller with the minimum design constraint gives us the best performance and energy consumption. We also run Monte Carlo simulation to show the estimated yield rate of the suggested design points.","Submission published under a 24 month embargo labeled 'Closed Access', the embargo will last until 2019-05-01","The student, David Min, accepted the attached license on 2017-04-10 at 11:14.","The student, David Min, submitted this Thesis for approval on 2017-04-10 at 11:15.","This Thesis was approved for publication on 2017-04-17 at 13:26.","DSpace SAF Submission Ingestion Package generated from Vireo submission #10674 on 2017-08-10 at 14:30:17","Made available in DSpace on 2017-08-10T19:51:47Z (GMT). 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