{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/95566"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/95566","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"Time-based control techniques for integrated DC-DC conversion","abstract":"Time-based control techniques for the design of high switching frequency buck converters are presented. Using time as the processing variable, the proposed controller operates with CMOS-level digital-like signals but without adding any quantization error. A ring oscillator is used as an integrator in place of conventional opamp-RC or Gm-C integrators while a delay line is used to perform voltage-to-time conversion and to sum time signals. A simple flip-flop generates a pulse-width modulated signal from the time-based output of the controller. Hence time-based control eliminates the need for a wide bandwidth error amplifier, pulse width modulator (PWM) in analog controllers or high-resolution analog-to-digital converter (ADC) and digital PWM in digital controllers. As a result, it can be implemented in a small area and with minimal power. First, a time-based single-phase buck converter is proposed and fabricated in a 180nm CMOS process, the prototype buck converter occupies an active area of 0.24mm^2, of which the controller occupies only 0.0375mm^2. It operates over a wide range of switching frequencies (10-25 MHz) and regulates output to any desired voltage in the range of 0.6V to 1.5V with 1.8V input voltage. With a 500mA step in the load current, the settling time is less than 3.5us and the measured reference tracking bandwidth is about 1MHz. Better than 94% peak efficiency is achieved while consuming a quiescent current of only 2uA/MHz. Second, the techniques are extended to a high switching frequency multi-phase buck converter. Efficiency degradation due to mismatch between the phases is mitigated by generating precisely matched duty-cycles by combining a time-based multi-phase generator (MPG) with a time-based PID compensator (T-PID). The proposed approach obviates the need for a complex current sensing and calibration circuitry needed to implement active current sharing in an analog controller. It also eliminates the need for a high-resolution analog-to-digital converter and digital pulse width modulator needed for implementing passive current sharing in a digital controller. Fabricated in a 65nm CMOS process, the prototype multi-phase buck converter occupies an active area of 0.32mm^2, of which the controller occupies only 0.04mm^2. The converter operates over a wide range of switching frequencies (30-70 MHz) and regulates output to any desired voltage in the range of 0.6V to 1.5V from 1.8V input voltage. With a 400mA step in the load current, the settling time is less than 0.6us and the measured duty-cycle mismatch is less than 0.48%. Better than 87% peak efficiency is achieved while consuming a quiescent current of only 3uA/MHz. Finally, light load operation is discussed. The light load efficiency of a time-based buck converter is improved by adding proposed PFM control. At the same time, the proposed seamless transition techniques provide a freedom to change the control mode between PFM and PWM without deteriorating output voltage which allows for a system to manage its power efficiently. Fabricated in a 65nm CMOS, the prototype achieves 90% peak efficiency and > 80% efficiency over an ILOAD range of 2mA to 800mA. VO changes by less than 40mV during PWM to PFM transitions.","abstract_html":"Time-based control techniques for the design of high switching frequency buck converters are presented. Using time as the processing variable, the proposed controller operates with CMOS-level digital-like signals but without adding any quantization error. A ring oscillator is used as an integrator in place of conventional opamp-RC or Gm-C integrators while a delay line is used to perform voltage-to-time conversion and to sum time signals. A simple flip-flop generates a pulse-width modulated signal from the time-based output of the controller. Hence time-based control eliminates the need for a wide bandwidth error amplifier, pulse width modulator (PWM) in analog controllers or high-resolution analog-to-digital converter (ADC) and digital PWM in digital controllers. As a result, it can be implemented in a small area and with minimal power. First, a time-based single-phase buck converter is proposed and fabricated in a 180nm CMOS process, the prototype buck converter occupies an active area of 0.24mm^2, of which the controller occupies only 0.0375mm^2. It operates over a wide range of switching frequencies (10-25 MHz) and regulates output to any desired voltage in the range of 0.6V to 1.5V with 1.8V input voltage. With a 500mA step in the load current, the settling time is less than 3.5us and the measured reference tracking bandwidth is about 1MHz. Better than 94% peak efficiency is achieved while consuming a quiescent current of only 2uA/MHz. Second, the techniques are extended to a high switching frequency multi-phase buck converter. Efficiency degradation due to mismatch between the phases is mitigated by generating precisely matched duty-cycles by combining a time-based multi-phase generator (MPG) with a time-based PID compensator (T-PID). The proposed approach obviates the need for a complex current sensing and calibration circuitry needed to implement active current sharing in an analog controller. It also eliminates the need for a high-resolution analog-to-digital converter and digital pulse width modulator needed for implementing passive current sharing in a digital controller. Fabricated in a 65nm CMOS process, the prototype multi-phase buck converter occupies an active area of 0.32mm^2, of which the controller occupies only 0.04mm^2. The converter operates over a wide range of switching frequencies (30-70 MHz) and regulates output to any desired voltage in the range of 0.6V to 1.5V from 1.8V input voltage. With a 400mA step in the load current, the settling time is less than 0.6us and the measured duty-cycle mismatch is less than 0.48%. Better than 87% peak efficiency is achieved while consuming a quiescent current of only 3uA/MHz. Finally, light load operation is discussed. The light load efficiency of a time-based buck converter is improved by adding proposed PFM control. At the same time, the proposed seamless transition techniques provide a freedom to change the control mode between PFM and PWM without deteriorating output voltage which allows for a system to manage its power efficiently. Fabricated in a 65nm CMOS, the prototype achieves 90% peak efficiency and > 80% efficiency over an ILOAD range of 2mA to 800mA. VO changes by less than 40mV during PWM to PFM transitions.","abstract_has_math":false,"creators":["Kim, Seong Joong"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"Ph.D.","degree_level":"Dissertation","degree_discipline":"Electrical & Computer Engr","degree_department":null,"school":null,"contributors":["Hanumolu, Pavan Kumar","Krein, Philip T.","Shanbhag, Naresh R.","Pilawa-Podgurski, Robert"],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2017,"date_issued":"2017-03-01T17:01:13Z","date_published":"2017-03-01T17:01:13Z","updated_at":"2026-07-22T22:26:37Z","subjects":["time-based","DC-DC","buck","Proportional-Integral-Derivative (PID)","Pulse-width modulator (PWM)","Pulse frequency modulation (PFM)"],"languages":["en"],"rights":["Copyright 2016 Seong Joong Kim"],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"http://hdl.handle.net/2142/95566","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Hanumolu, Pavan Kumar","Krein, Philip T.","Shanbhag, Naresh R.","Pilawa-Podgurski, Robert"]},{"key":"dc:creator","label":"Author","values":["Kim, Seong Joong"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2017-03-01T17:01:13Z","2019-03-02T10:15:33Z","2016-11-09","2016-12"]},{"key":"dc:type","label":"Dc Type","values":["text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical & Computer Engr"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Dissertation"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Ph.D."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["time-based","DC-DC","buck","Proportional-Integral-Derivative (PID)","Pulse-width modulator (PWM)","Pulse frequency modulation (PFM)"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["en"]},{"key":"dc:rights","label":"Dc Rights","values":["Copyright 2016 Seong Joong Kim"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["http://hdl.handle.net/2142/95566"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["Time-based control techniques for the design of high switching frequency buck converters are presented. Using time as the processing variable, the proposed controller operates with CMOS-level digital-like signals but without adding any quantization error. A ring oscillator is used as an integrator in place of conventional opamp-RC or Gm-C integrators while a delay line is used to perform voltage-to-time conversion and to sum time signals. A simple flip-flop generates a pulse-width modulated signal from the time-based output of the controller. Hence time-based control eliminates the need for a wide bandwidth error amplifier, pulse width modulator (PWM) in analog controllers or high-resolution analog-to-digital converter (ADC) and digital PWM in digital controllers. As a result, it can be implemented in a small area and with minimal power. First, a time-based single-phase buck converter is proposed and fabricated in a 180nm CMOS process, the prototype buck converter occupies an active area of 0.24mm^2, of which the controller occupies only 0.0375mm^2. It operates over a wide range of switching frequencies (10-25 MHz) and regulates output to any desired voltage in the range of 0.6V to 1.5V with 1.8V input voltage. With a 500mA step in the load current, the settling time is less than 3.5us and the measured reference tracking bandwidth is about 1MHz. Better than 94% peak efficiency is achieved while consuming a quiescent current of only 2uA/MHz. Second, the techniques are extended to a high switching frequency multi-phase buck converter. Efficiency degradation due to mismatch between the phases is mitigated by generating precisely matched duty-cycles by combining a time-based multi-phase generator (MPG) with a time-based PID compensator (T-PID). The proposed approach obviates the need for a complex current sensing and calibration circuitry needed to implement active current sharing in an analog controller. It also eliminates the need for a high-resolution analog-to-digital converter and digital pulse width modulator needed for implementing passive current sharing in a digital controller. Fabricated in a 65nm CMOS process, the prototype multi-phase buck converter occupies an active area of 0.32mm^2, of which the controller occupies only 0.04mm^2. The converter operates over a wide range of switching frequencies (30-70 MHz) and regulates output to any desired voltage in the range of 0.6V to 1.5V from 1.8V input voltage. With a 400mA step in the load current, the settling time is less than 0.6us and the measured duty-cycle mismatch is less than 0.48%. Better than 87% peak efficiency is achieved while consuming a quiescent current of only 3uA/MHz. Finally, light load operation is discussed. The light load efficiency of a time-based buck converter is improved by adding proposed PFM control. At the same time, the proposed seamless transition techniques provide a freedom to change the control mode between PFM and PWM without deteriorating output voltage which allows for a system to manage its power efficiently. Fabricated in a 65nm CMOS, the prototype achieves 90% peak efficiency and > 80% efficiency over an ILOAD range of 2mA to 800mA. VO changes by less than 40mV during PWM to PFM transitions.","Submission published under a 24 month embargo labeled 'Closed Access', the embargo will last until 2018-12-01","The student, Seong Joong Kim, accepted the attached license on 2016-11-08 at 17:34.","The student, Seong Joong Kim, submitted this Dissertation for approval on 2016-11-08 at 17:35.","This Dissertation was approved for publication on 2016-11-09 at 15:08.","DSpace SAF Submission Ingestion Package generated from Vireo submission #10226 on 2017-02-28 at 14:41:24","Made available in DSpace on 2017-03-01T17:01:13Z (GMT). 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Using time as the processing variable, the proposed controller operates with CMOS-level digital-like signals but without adding any quantization error. A ring oscillator is used as an integrator in place of conventional opamp-RC or Gm-C integrators while a delay line is used to perform voltage-to-time conversion and to sum time signals. A simple flip-flop generates a pulse-width modulated signal from the time-based output of the controller. Hence time-based control eliminates the need for a wide bandwidth error amplifier, pulse width modulator (PWM) in analog controllers or high-resolution analog-to-digital converter (ADC) and digital PWM in digital controllers. As a result, it can be implemented in a small area and with minimal power. First, a time-based single-phase buck converter is proposed and fabricated in a 180nm CMOS process, the prototype buck converter occupies an active area of 0.24mm^2, of which the controller occupies only 0.0375mm^2. It operates over a wide range of switching frequencies (10-25 MHz) and regulates output to any desired voltage in the range of 0.6V to 1.5V with 1.8V input voltage. With a 500mA step in the load current, the settling time is less than 3.5us and the measured reference tracking bandwidth is about 1MHz. Better than 94% peak efficiency is achieved while consuming a quiescent current of only 2uA/MHz. Second, the techniques are extended to a high switching frequency multi-phase buck converter. Efficiency degradation due to mismatch between the phases is mitigated by generating precisely matched duty-cycles by combining a time-based multi-phase generator (MPG) with a time-based PID compensator (T-PID). The proposed approach obviates the need for a complex current sensing and calibration circuitry needed to implement active current sharing in an analog controller. It also eliminates the need for a high-resolution analog-to-digital converter and digital pulse width modulator needed for implementing passive current sharing in a digital controller. Fabricated in a 65nm CMOS process, the prototype multi-phase buck converter occupies an active area of 0.32mm^2, of which the controller occupies only 0.04mm^2. The converter operates over a wide range of switching frequencies (30-70 MHz) and regulates output to any desired voltage in the range of 0.6V to 1.5V from 1.8V input voltage. With a 400mA step in the load current, the settling time is less than 0.6us and the measured duty-cycle mismatch is less than 0.48%. Better than 87% peak efficiency is achieved while consuming a quiescent current of only 3uA/MHz. Finally, light load operation is discussed. The light load efficiency of a time-based buck converter is improved by adding proposed PFM control. At the same time, the proposed seamless transition techniques provide a freedom to change the control mode between PFM and PWM without deteriorating output voltage which allows for a system to manage its power efficiently. Fabricated in a 65nm CMOS, the prototype achieves 90% peak efficiency and > 80% efficiency over an ILOAD range of 2mA to 800mA. VO changes by less than 40mV during PWM to PFM transitions.","Submission published under a 24 month embargo labeled 'Closed Access', the embargo will last until 2018-12-01","The student, Seong Joong Kim, accepted the attached license on 2016-11-08 at 17:34.","The student, Seong Joong Kim, submitted this Dissertation for approval on 2016-11-08 at 17:35.","This Dissertation was approved for publication on 2016-11-09 at 15:08.","DSpace SAF Submission Ingestion Package generated from Vireo submission #10226 on 2017-02-28 at 14:41:24","Made available in DSpace on 2017-03-01T17:01:13Z (GMT). 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