{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/95447"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/95447","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"Protocol-directed trace signal selection for post-silicon validation","abstract":"Due to the increasing complexity of modern digital designs using NoC (network-on-chip) communication, post-silicon validation has become an arduous task that consumes much of the development time of the product. The process of finding the root cause of bugs during post-silicon validation is very difficult because of the lack of observability of all signals on the chip. To increase observability for post-silicon validation, an effective silicon debug technique is to use an on-chip trace buffer to monitor and capture the circuit response of certain selected signals during its post-silicon operation. However, because of area limitations for debug structures on chip and routing concerns, the signals that are selected to be traced are a very small subset of all available signals. Traditionally, these trace signals were chosen manually by system designers who determined what signals may be needed for debug once the design reaches post-silicon. However, because modern digital designs have become very complex with many concurrent processes, this method is no longer reliable. Recent work has concentrated on automating the selection of low-level signals from a gate-level analysis. But none of them has ever been able to interpret the trace signals as high-level meaningful debugging information. In this work, we present an automated protocol-directed trace selection where the guiding force is the set of system-level protocols. We use a probabilistic formulation to select messages for tracing and then further analyze these solutions. This method produces traces that allow a debugger to observe when behavior has deviated from the correct path of execution and localize this incorrect behavior for further analysis. Most importantly, unlike the previous gate-level analysis based methods, this method can be applied during the chip design phase when most of the debug features are also designed. In addition, this method drastically reduces the time needed to select signals, as we automate a currently manual process.","abstract_html":"Due to the increasing complexity of modern digital designs using NoC (network-on-chip) communication, post-silicon validation has become an arduous task that consumes much of the development time of the product. The process of finding the root cause of bugs during post-silicon validation is very difficult because of the lack of observability of all signals on the chip. To increase observability for post-silicon validation, an effective silicon debug technique is to use an on-chip trace buffer to monitor and capture the circuit response of certain selected signals during its post-silicon operation. However, because of area limitations for debug structures on chip and routing concerns, the signals that are selected to be traced are a very small subset of all available signals. Traditionally, these trace signals were chosen manually by system designers who determined what signals may be needed for debug once the design reaches post-silicon. However, because modern digital designs have become very complex with many concurrent processes, this method is no longer reliable. Recent work has concentrated on automating the selection of low-level signals from a gate-level analysis. But none of them has ever been able to interpret the trace signals as high-level meaningful debugging information. In this work, we present an automated protocol-directed trace selection where the guiding force is the set of system-level protocols. We use a probabilistic formulation to select messages for tracing and then further analyze these solutions. This method produces traces that allow a debugger to observe when behavior has deviated from the correct path of execution and localize this incorrect behavior for further analysis. Most importantly, unlike the previous gate-level analysis based methods, this method can be applied during the chip design phase when most of the debug features are also designed. In addition, this method drastically reduces the time needed to select signals, as we automate a currently manual process.","abstract_has_math":false,"creators":["Sharma, Abhishek"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"M.S.","degree_level":"Thesis","degree_discipline":"Electrical & Computer Engr","degree_department":null,"school":null,"contributors":["Vasudevan, Shobha"],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2017,"date_issued":"2017-03-01T16:36:37Z","date_published":"2017-03-01T16:36:37Z","updated_at":"2026-07-22T22:26:37Z","subjects":["Post-silicon validation"],"languages":["en"],"rights":["Copyright 2016 Abhishek Sharma"],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"http://hdl.handle.net/2142/95447","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Vasudevan, Shobha"]},{"key":"dc:creator","label":"Author","values":["Sharma, Abhishek"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2017-03-01T16:36:37Z","2019-03-02T10:15:24Z","2016-08-04","2016-12"]},{"key":"dc:type","label":"Dc Type","values":["text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical & Computer Engr"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Thesis"]},{"key":"thesis:degree_name","label":"Degree Name","values":["M.S."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Post-silicon validation"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["en"]},{"key":"dc:rights","label":"Dc Rights","values":["Copyright 2016 Abhishek Sharma"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["http://hdl.handle.net/2142/95447"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["Due to the increasing complexity of modern digital designs using NoC (network-on-chip) communication, post-silicon validation has become an arduous task that consumes much of the development time of the product. The process of finding the root cause of bugs during post-silicon validation is very difficult because of the lack of observability of all signals on the chip. To increase observability for post-silicon validation, an effective silicon debug technique is to use an on-chip trace buffer to monitor and capture the circuit response of certain selected signals during its post-silicon operation. However, because of area limitations for debug structures on chip and routing concerns, the signals that are selected to be traced are a very small subset of all available signals. Traditionally, these trace signals were chosen manually by system designers who determined what signals may be needed for debug once the design reaches post-silicon. However, because modern digital designs have become very complex with many concurrent processes, this method is no longer reliable. Recent work has concentrated on automating the selection of low-level signals from a gate-level analysis. But none of them has ever been able to interpret the trace signals as high-level meaningful debugging information. In this work, we present an automated protocol-directed trace selection where the guiding force is the set of system-level protocols. We use a probabilistic formulation to select messages for tracing and then further analyze these solutions. This method produces traces that allow a debugger to observe when behavior has deviated from the correct path of execution and localize this incorrect behavior for further analysis. Most importantly, unlike the previous gate-level analysis based methods, this method can be applied during the chip design phase when most of the debug features are also designed. In addition, this method drastically reduces the time needed to select signals, as we automate a currently manual process.","Submission published under a 24 month embargo labeled 'U of I Access', the embargo will last until 2018-12-01","The student, Abhishek Sharma, accepted the attached license on 2016-08-03 at 12:39.","The student, Abhishek Sharma, submitted this Thesis for approval on 2016-08-03 at 13:03.","This Thesis was approved for publication on 2016-08-04 at 11:15.","DSpace SAF Submission Ingestion Package generated from Vireo submission #10102 on 2017-02-28 at 14:35:51","Made available in DSpace on 2017-03-01T16:36:37Z (GMT). No. of bitstreams: 6 SHARMA-THESIS-2016.pdf: 2786195 bytes, checksum: faa35db071f1018cfd94fd90d2cec34c (MD5) abs.tex: 2033 bytes, checksum: d000fe6a692891de0f30edf44fd0b4f5 (MD5) ack.tex: 1006 bytes, checksum: bf151b5672ddfe6580c57d71f034a2a9 (MD5) apx.tex: 1543 bytes, checksum: 28ff671e8839f1eee4e148520591c7a7 (MD5) ecethesis.tex: 114440 bytes, checksum: 4bbfaf28458e404d211ce219aa3f8633 (MD5) LICENSE.txt: 4212 bytes, checksum: 3bff1fdb1c67b5cba6db1fdd94091319 (MD5) Previous issue date: 2016-08-04","Embargo set by: Seth Robbins for item 98563 Lift date: 2019-03-01T16:37:19Z Reason: Author requested U of Illinois access only (OA after 2yrs) in Vireo ETD system","U of I Only Restriction Lifted for Item 98563 on 2019-03-02T10:15:24Z."]},{"key":"dc:format","label":"Dc Format","values":["application/pdf"]},{"key":"dc:title","label":"Title","values":["Protocol-directed trace signal selection for post-silicon validation"]}]}],"canonical_facts":{"dc:contributor":["Vasudevan, Shobha"],"dc:creator":["Sharma, Abhishek"],"dc:date":["2017-03-01T16:36:37Z","2019-03-02T10:15:24Z","2016-08-04","2016-12"],"dc:description":["Due to the increasing complexity of modern digital designs using NoC (network-on-chip) communication, post-silicon validation has become an arduous task that consumes much of the development time of the product. The process of finding the root cause of bugs during post-silicon validation is very difficult because of the lack of observability of all signals on the chip. To increase observability for post-silicon validation, an effective silicon debug technique is to use an on-chip trace buffer to monitor and capture the circuit response of certain selected signals during its post-silicon operation. However, because of area limitations for debug structures on chip and routing concerns, the signals that are selected to be traced are a very small subset of all available signals. Traditionally, these trace signals were chosen manually by system designers who determined what signals may be needed for debug once the design reaches post-silicon. However, because modern digital designs have become very complex with many concurrent processes, this method is no longer reliable. Recent work has concentrated on automating the selection of low-level signals from a gate-level analysis. But none of them has ever been able to interpret the trace signals as high-level meaningful debugging information. In this work, we present an automated protocol-directed trace selection where the guiding force is the set of system-level protocols. We use a probabilistic formulation to select messages for tracing and then further analyze these solutions. This method produces traces that allow a debugger to observe when behavior has deviated from the correct path of execution and localize this incorrect behavior for further analysis. Most importantly, unlike the previous gate-level analysis based methods, this method can be applied during the chip design phase when most of the debug features are also designed. In addition, this method drastically reduces the time needed to select signals, as we automate a currently manual process.","Submission published under a 24 month embargo labeled 'U of I Access', the embargo will last until 2018-12-01","The student, Abhishek Sharma, accepted the attached license on 2016-08-03 at 12:39.","The student, Abhishek Sharma, submitted this Thesis for approval on 2016-08-03 at 13:03.","This Thesis was approved for publication on 2016-08-04 at 11:15.","DSpace SAF Submission Ingestion Package generated from Vireo submission #10102 on 2017-02-28 at 14:35:51","Made available in DSpace on 2017-03-01T16:36:37Z (GMT). No. of bitstreams: 6 SHARMA-THESIS-2016.pdf: 2786195 bytes, checksum: faa35db071f1018cfd94fd90d2cec34c (MD5) abs.tex: 2033 bytes, checksum: d000fe6a692891de0f30edf44fd0b4f5 (MD5) ack.tex: 1006 bytes, checksum: bf151b5672ddfe6580c57d71f034a2a9 (MD5) apx.tex: 1543 bytes, checksum: 28ff671e8839f1eee4e148520591c7a7 (MD5) ecethesis.tex: 114440 bytes, checksum: 4bbfaf28458e404d211ce219aa3f8633 (MD5) LICENSE.txt: 4212 bytes, checksum: 3bff1fdb1c67b5cba6db1fdd94091319 (MD5) Previous issue date: 2016-08-04","Embargo set by: Seth Robbins for item 98563 Lift date: 2019-03-01T16:37:19Z Reason: Author requested U of Illinois access only (OA after 2yrs) in Vireo ETD system","U of I Only Restriction Lifted for Item 98563 on 2019-03-02T10:15:24Z."],"dc:format":["application/pdf"],"dc:identifier":["http://hdl.handle.net/2142/95447"],"dc:language":["en"],"dc:rights":["Copyright 2016 Abhishek Sharma"],"dc:subject":["Post-silicon validation"],"dc:title":["Protocol-directed trace signal selection for post-silicon validation"],"dc:type":["text"],"thesis:degree_discipline":["Electrical & Computer Engr"],"thesis:degree_level":["Thesis"],"thesis:degree_name":["M.S."],"thesis:institution_name":["University of Illinois at Urbana-Champaign"]},"updated_at":"2026-07-22T22:26:37Z"}